Abstract: A memory system, a memory controller and an operating method of the memory controller. The memory controller may include a host interface configured to communicate with a host; a memory interface configured to communicate with a memory device; and a control circuit configured to control an operation of the memory device. The control circuit may selectively determine to use a cache for an operation indicated by a command received from the host, depending on a number of memory dies, of a plurality of memory dies in the memory device, detected to be in an activated state.

Abstract: A data storage device includes: a non-volatile memory device, a random access memory and a processor. The non-volatile memory device stores a plurality of L2P entries related to a plurality of logical addresses. The random access memory stores a sequential flag table including sequential flags for a plurality of sequential segments. Each of the sequential flags are flags representing whether physical addresses corresponding to the logical addresses of the sequential segments are sequential or not. The processor identifies a sequential flag of a sequential segment related to read logical address information based on the sequential flag table. The processor reads at least one of the L2P entries, which are correspond to the read logical address information based on the sequential flag and loads the read L2P entry into the random access memory.

Abstract: A method for operating a memory system includes checking, by a memory device manager, an available capacity of a memory device in response to a write request transmitted from a host device; determining, by the memory device manager, a parallel access size based on the available capacity; comparing, by the memory device manager, a size of host data to be written in one or more nonvolatile memory devices in response to the write request, with the available capacity; receiving, by the memory device manager, host data of a first size in the memory device from the host device; and writing, by an access unit, the host data received in the memory device, to the nonvolatile memory devices by a unit of the parallel access size.

Abstract: A memory system includes a nonvolatile memory device; a random access memory configured to store, in response to an unmap request received from a host device, a flag information indicating that an unmap address as a target of the unmap request is unmapped; and a control unit configured to flush the flag information to the nonvolatile memory device, wherein the control unit flushes the flag information to the nonvolatile memory device when a first condition is satisfied.

Abstract: A memory system includes a plurality of memory devices, each including a plurality of memory blocks; and a controller configured to evaluate performance grades of the plurality of memory blocks, form super blocks spanning the plurality of memory devices by selecting memory blocks, among the plurality of memory blocks, to be included in each of the super blocks based on the performance grades, and write-access an opened super block, among the super blocks.

Abstract: A controller includes: a processor suitable for controlling a memory device to read map data stored in a memory and read out a physical address corresponding to data requested by a host to be read; a counter suitable for obtaining reliability information on the map data stored in the memory; a determining unit suitable for activating a pre-pumping mode when reliability of the map data is poor; a deciding unit suitable for determining a first target die of a pre-pumping operation for reading the data in the activated pre-pumping mode; and a pumping unit suitable for controlling the memory device to perform the pre-pumping operation on the first target die during a background operation for reading out the physical address.

Abstract: A data storage device may include: a nonvolatile memory device; and a controller configured to control an operation of the nonvolatile memory device. In response to an unmap command is received from a host, the controller may generate an unmap descriptor including logical block addresses to be trimmed, stores the generated unmap descriptor, and transfer a response signal to the host. The response signal indicates that an unmap caching operation corresponding to the unmap command is completed.

Abstract: Methods, systems and devices for efficiently performing a read fail recovery operation are described. An exemplary data storage device includes a nonvolatile memory device including a page group in which program-completed pages and program-in-progress pages are mixed, a buffer memory configured to buffer data and an XOR parity to be stored in pages of the page group. The data storage device also includes a recovery circuit configured to recover an error of read-failed data, and a processor configured to control the recovery circuit to read data and an XOR parity corresponding to the program-in-progress pages from the buffer memory. The processor is also configured to recover the error of the read-failed data using data corresponding to remaining program-completed pages other than a page in which the read-failed data is stored among the program-completed pages, and the data and the XOR parity read from the buffer memory.

Abstract: A memory system includes a nonvolatile memory device; a random access memory configured to store, in response to an unmap request received from a host device, a flag information indicating that an unmap address as a target of the unmap request is unmapped; and a control unit configured to flush the flag information to the nonvolatile memory device, wherein the control unit flushes the flag information to the nonvolatile memory device when a first condition is satisfied.

Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device includes a memory controller having a map manager and preload mapping information storage, and a memory device having logical-to-physical mapping information. The memory controller determines and obtains from the memory device, preloads mapping information, and then stores the preload mapping information in the preload mapping information storage, before a map update operation of the logical-to-physical mapping information is performed. The preload mapping information includes logical-to-physical mapping information to be updated.

Abstract: A memory system includes a memory device for storing first and second mapping information associated with target logical addresses for an unmap command, and a controller for loading the first and second mapping information from the memory device, comparing a size of target map data corresponding to the target logical addresses with a threshold value, sorting a plurality of map segments mapped with a plurality of target logical groups including the target logical addresses, respectively, into a plurality of regions based on a result of the comparing, and performing an unmap operation on each of the map segments included in the regions, wherein the first mapping information includes information on mapping relationships between the plurality of map segments and the plurality of target logical groups, and the second mapping information includes information on mapping relationships between the target logical addresses and corresponding physical addresses.

Abstract: A data storage apparatus includes a nonvolatile memory device including block groups, a random access memory including a sequential map table that stores a sequential map entry for consecutive sequential write logical addresses, among write addresses received from a host apparatus, greater than or equal to a predetermined threshold number, and a processor configured to determine whether or not first sequential write logical addresses are present among logical addresses corresponding to physical addresses for a first region of a first block group when a write operation for the first region of the first block group in response to a write request received from the host apparatus is completed, generate a first sequential map entry for the first sequential write logical addresses when the first sequential write logical addresses are present, and store the first sequential map entry in the sequential map table.

Abstract: A multilayer capacitor includes a body including a stacked structure formed of a plurality of dielectric layers, and a plurality of internal electrodes, and external electrodes, wherein the body is divided into a central portion, and cover portions, the body has first to sixth surfaces, in the body, the cover portion forms corner edges having a curved surface, and if a radius of curvature of each of the corner edges at which the third and fourth surfaces meet the fifth and sixth surfaces refers to R1, and a radius of curvature of each of the corner edges at which the third and fourth surfaces meet the first and second surfaces refers to R2, a relationship of R1>R2 is satisfied, and a width of an internal electrode disposed in the cover portion is narrower than a width of an internal electrode disposed in the central portion.

Abstract: A multilayer capacitor includes a body including a stacked structure having dielectric layers, and internal electrodes, and external electrodes. The body has a central portion, and cover portions disposed above and below the central portion, the body has a first surface and a second surface to which the internal electrodes are exposed and which oppose each other, a third surface and a fourth surface which oppose each other in the stacking direction of the dielectric layers, and a fifth surface and a sixth surface which are connected to the first to fourth surfaces and oppose each other, and a surface roughness of each of the third to sixth surfaces of the body is greater than a surface roughness of each of the first and second surfaces of the body.

Abstract: The present disclosure provides a cosmetic including a cosmetic composition having low viscosity, a receiving member in which the cosmetic composition having low viscosity is received, and a film forming member which covers an opening of the receiving member. By the use of the elastic film forming member, the cosmetic of the present disclosure may provide convenience of carrying with, reduce the container volume, and increase an amount of cosmetic composition contained, as compared to sponge impregnation material cosmetics.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include: a semiconductor memory device to which an address mapping table including a plurality of map segments is stored; and a controller configured to load and store, during a read operation, one or more map segments selected from among the plurality of map segments. The controller may include: a compression engine configured to compress the one or more map segments and generate one or more compressed map segments and metadata corresponding thereto; a map data loading buffer configured to store the one or more compressed map segments and the metadata; and a processor configured to store the one or more compressed map segments to a random access memory (RAM) using the metadata.

Abstract: Provided herein may be a storage device and a method of operating the same. A method of operating a memory controller Included in a storage device for processing an unmap request may include receiving an unmap request for requesting deletion of address mapping information for an unmap address from a host, storing the unmap address and prestored unmap-pattern data in a random access memory (RAM), and outputting the unmap-pattern data to the host in response to a read request for the unmap address being inputted.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The method may include: receiving an unmap command corresponding to logical addresses; setting a state of at least one unmap bit corresponding to the logical addresses among a plurality of unmap bits included in an unmap filter to an unmapped state in response to the unmap command; and setting a state of logical-to-physical address mapping information about a logical address, among the logical addresses, that does not correspond to the at least one unmap bit to an unmapped state.

Abstract: A multilayer capacitor includes a body, a plurality of internal electrodes and external electrodes disposed on external surfaces of the body and electrically connected to the internal electrodes, wherein in the body, corners of cover portions include curved surfaces, and 10 ?m?R?T/4 in which R is a radius of curvature of the curved surface corners and T is a thickness of the body, and when a distance from a surface of the body to an internal electrode closest to the surface of the body among the plurality of internal electrodes is a margin, a margin (?) of each of the corners formed as the curved surfaces in the cover portions is greater than or equal to a margin (Wg) of the body in a width direction.

Abstract: A multilayer capacitor includes a body, a plurality of internal electrodes, and external electrodes. The corners of the cover portions of the body include curved surfaces, a length of each of internal electrodes disposed in the cover portions among the plurality of internal electrodes is smaller than a length of an internal electrode disposed in a central portion, and when a distance from a surface of the body to a closest internal electrode among the plurality of internal electrodes is defined as a margin, a margin Wg of each of the fifth surface and the sixth surface and a margin Tg of each of the third surface and the fourth surface satisfy a condition of 0.8?Tg/Wg?1.2.