Abstract: The present invention relates to a circuit board carrier including a carrier sliding between a conveyor and a holder disposed at the lower part of a main machine. The carrier includes a sliding rail disposed at the top of a main machine above the conveyor and the holder; a sliding base being on the sliding rail by means of a sliding recess thereof; a sliding rod disposed above the sliding base and being vertically spaced to the sliding rail; a sliding seat being slid on the sliding rod by means of a sliding piece and having a shaft post at the top thereof; a pivot sleeve pivoted on the shaft post of the sliding seat by means of a bearing thereof and having a connection groove; a turning arm, one end of which is connected to the connection groove of the pivot sleeve while the other end thereof is connected to a motor and a driving axle of a reduction machine; and a suction unit installed under the sliding base.

Abstract: A method for forming through a microelectronic layer a via contiguous with a trench. There is first provided a substrate. There is then formed over the substrate a first microelectronic layer. There is then formed upon the first microelectronic layer an etch stop layer. There is then formed upon the etch stop layer a second microelectronic layer. There is then formed over the second microelectronic layer a first patterned photoresist layer which defines the location of a via to be formed through the second microelectronic layer, the etch stop layer and the first microelectronic layer. There is then etched, while employing a first etch method which employs the first patterned photoresist layer as a first etch mask layer, the second microelectronic layer, the etch stop layer and the first microelectronic layer to form a corresponding patterned second microelectronic layer, patterned etch stop layer and patterned first microelectronic layer which define the via.

Abstract: A method for forming within a deep ultraviolet (DUV) sensitive photosensitive layer formed upon a substrate employed within a microelectronics fabrication a pattern with attenuated defects and improved strippability. There is provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a photosensitive layer formed of an organic polymer resin plus additives which is sensitive to deep ultraviolet (DUV) irradiation. There is then formed within the photosensitive layer a patterned latent image by selective irradiation with a deep ultraviolet (DUV) source. There is then developed the latent image by successive treatment of the photosensitive layer to a first developer agent at a first concentration and a second developer agent at a second concentration, interspersed with aqueous solvent rinses, to form a patterned photoresist layer with attenuated residues.

Abstract: A new method is provided for the alignment of the patterning of AlCu pads in an environment of copper interconnect line patterns. A layer of passivation material is deposited over a surface that contains alignment marks. The layer of passivation is patterned creating in the surface of the layer of passivation the opening that is required for the AlCu pad in addition to openings for a new pattern of alignment marks. A layer of AlCu is sputter deposited over the surface of the layer of passivation thereby including the openings that have been created in the layer of passivation. This creates a new pattern of alignment marks in the surface of the deposited layer of AlCu whereby these new alignment marks align with the pattern of new alignment marks that has been etched in the layer of passivation. The new alignment marks are then used to pattern the layer of AlCu for the creation of the AlCu pad.

Abstract: A new process for fabricating a phase-shifting photomask is described. A photomask blank is provided comprising a chromium layer overlying a substrate and a resist layer overlying said chromium layer. The resist layer of the photomask blank is exposed to electron-beam energy and developed away whereby a first resist pattern remains. The chromium layer not covered by the first resist pattern is etched away and, simultaneously, the substrate not covered by the first resist pattern is etched into to a depth in namometers of ¼ the wavelength of the exposure tool whereby a substrate step is formed underlying the first resist pattern. Thereafter, a portion of the first resist pattern is ashed away to leave a second resist pattern smaller than the first resist pattern and exposing portions of the chromium layer underlying the first resist pattern. The exposed portions of the chromium layer not covered by the second resist pattern are etched away whereby portions of the underlying substrate step are exposed.

Abstract: A tool for placing an identifying mark on a semiconductor wafer has a bundle of optical fibers that can be illuminated in a pattern representing an identifying character. Light from the fibers is focused on a photoresist layer during wafer manufacture and a pattern of dots is etched into the wafer to represent the character. The dots are too small to be seen with the human eye but the character can be read by a human or by a machine. The character is etched as part of a conventional etch step in manufacturing the wafer and it is easily repeated as a series of manufacturing steps obscure the original mark.

Abstract: A new method is provided of trench etching of the dual damascene structure. The invention replaces the conventional ARC deposition with the deposition of I-line photoresist. The I-line photoresist serves as an anti reflective coating and eliminates, for small opening size, the problems that are encountered with conventional ARC. The deposition characteristics of the I-line photoresist can be adjusted by pre-baking the I-line photoresist prior to deposition thereby controlling its viscosity and density.

Abstract: Jogs are sometimes needed in lines that are used as wires in integrated circuits. In the prior art, these jogs are introduced by inserting a diagonal segment at the desired location. This type of shape is expensive to generate when electron beam writing is used. In the present invention the problem is solved by forming the jog through a simple lateral sliding of two halves of the line relative to one another. The resulting line pattern has both sharp corners and a central constriction but when it is transferred to photoresist, using standard photolithographic techniques, both the sharp corners and the constriction are no longer present, provided no OPC was applied to that section of the line. The motivation for this is the much lower cost of E-beam drawing for the structure of the present invention relative to structures of the prior art.

Abstract: A tool and method for placing an identifying mark on a semiconductor wafer has a bundle of optical fibers that can be illuminated in a pattern representing an identifying character. Light from the fibers is focused on a photoresist layer during wafer manufacture and a pattern of dots is etched into the wafer to represent the character. The dots are too small to be seen with the human eye but the character can be read by a human or by a machine. The character is etched as part of a conventional etch step in manufacturing the wafer and it is easily repeated as a series of manufacturing steps obscure the original mark.

Abstract: A note pad includes a plurality of stacked self-stick transparent note sheets. Each of the note sheets includes a transparent plastic film coated with a transparent coating layer and a pressure-sensitive adhesive layer. The coating layer is prepared from a mixture of a binder and at least one pigment. The weight ratio of the binder to the pigment ranges from 1:1 to 1:10. Each of the note sheets has an opacity of less than 45%.

Abstract: An apparatus is adapted for picking-up an integrated circuit component and is adapted to be connected to an air pump. The apparatus includes a retaining block formed with a first pipe hole and a washer receiving recess for receiving a washer. An air pipe is formed with a radially and outwardly extending rim flange at a junction of upper and lower pipe sections thereof. The lower pipe section extends sealingly through a second pipe hole in the washer and further through the first pipe hole such that the rim flange rests on top of the washer in the washer receiving recess, such that a distal lower end of the lower pipe section projects downwardly relative to the retaining block, and such that a distal upper end of the upper pipe section extends outwardly of the washer receiving recess and projects upwardly relative to the retaining block.

Abstract: A local nonlinear feedback loop (LNFL) technique and a sigma-delta modulator (SDM) for promoting highly stable oversampling using the LNFL technique. Not only can gain mismatch of the sigma-delta modulator be minimized, but the overload of the later stage sigma-delta modulator can also be resolved without sacrificing the signal noise ratios (SNR) of the overall system. Moreover, using the local nonlinear feedback loop technique of this invention attenuates the voltage signal of the sigma-delta modulator, therefore decreasing the power consumption of the overall sigma-delta modulator system.

Abstract: A method is adapted to form wire interconnect pads on integrated circuit devices and includes the steps of providing a semiconductor substrate having an aluminum-copper top metal layer, and a titanium nitride layer covering the aluminum-copper top metal layer, and a photoresist coating applied to the titanium nitride layer. The photoresist coating is partially exposed and partially developed to form openings for etching an array of submicron size holes. Etching through the titanium nitride layer to the aluminum-copper layer, by way of the partially developed photoresist, forms a rough textured surface profile in the array of cavities, with diameters of less than 0.3 um, etched in the aluminum copper layer. After stripping of the photoresist and depositing a passivation film, windows are formed delineating improved bond pads for wire bonding. The textured cavities increase the surface area of the bond pads and provide improved bondability for the 0.35 and 0.3 um IC devices.

Abstract: A testing apparatus for testing a ball grid array (BGA) device, includes a movable carrier which has a top face recessed to form a cavity of square shape to receive the BGA device. A centering member is disposed at a center part of a cavity bottom face of the cavity to center a squarely looped array of voltage source solder balls formed at a bottom face of the BGA device, relative to the center part of the cavity bottom face. The centering member projects upward from the cavity bottom face to engage and prevent positional deviation of the squarely looped array of the voltage source solder balls when the BGA device is seated on the cavity bottom face. The testing apparatus further includes a testing circuit unit, a surface mount matrix disposed on top of the testing circuit unit, and a hollow frame member mounted on top of the surface mount matrix.

Abstract: A process is described for forming very narrow polysilicon gate lines for use as gate electrodes in FETs. The process uses a consumable hard mask of silicon oxynitride covered by a thin layer of silicon oxide during the etching of the polysilicon. The thicknesses of the two layers that make up the hard mask are chosen so that the structure also serves as an ARC for the photoresist coating immediately above it. A relatively thin layer of the latter is used in order to improve resolution. After the photoresist has been patterned it may be trimmed or it may be removed and re-formed, since the silicon oxide layer provides protection for the underlying silicon oxynitride. After the hard mask has been formed, all photoresist is removed and the polysilicon is etched. During etching there is simultaneous removal of the silicon oxide layer and part of the silicon oxynitride as well.

Abstract: The present invention discloses a method and system to encrypt an object code using a non-inversible transform and dynamic keys in an encryption circuit and an decryption circuit. The encryption circuit operates to encrypt an object code to an encrypted code using a sequence of dynamic keys which possess non-inversible transform characteristics. Similarly, the decryption circuit operates to decrypt the encrypt code using a sequence of dynamic keys which possess non-inversible transform characteristics. The sequence of dynamic keys change in accordance to a timing index in which a different key is generated for a different timing cycle. In one embodiment, the decryption circuit contains a transform circuit U to transform the encrypted code back to the object code. In another embodiment, the transform circuit U is partitioned into a resident device and mobile device.

Abstract: A method is adapted to form wire interconnect pads on integrated circuit devices and includes the steps of providing a semiconductor substrate having an aluminum-copper top metal layer, and a titanium nitride layer covering the aluminum-copper top metal layer, and a photoresist coating applied to the titanium nitride layer. The photoresist coating is partially exposed and partially developed to form openings for etching an array of submicron size holes. Etching through the titanium nitride layer to the aluminum-copper layer, by way of the partially developed photoresist, forms a rough textured surface profile in the array of cavities, with diameters of less than 0.3 um, etched in the aluminum copper layer. After stripping of the photoresist and depositing a passivation film, windows are formed delineating improved bond pads for wire bonding. The textured cavities increase the surface area of the bond pads and provide improved bondability for the 0.35 and 0.3 um IC devices.

Abstract: Improved etching of sub-micron diameter via or contact holes in integrated circuits is achieved by first coating the dielectric layer through which the hole is to be etched with successive layers of titanium and silicon oxynitride. This is followed by coating with a conventional photoresist mask which is thinner than usual, thereby allowing for improved resolution. Etching is carried out in two stages. First, only the oxynitride and titanium layers are etched with minimal penetration into the dielectric. In this way a hard mask of titanium is formed. It's optical fidelity is excellent since the combination of silicon oxynitride and titanium act as a very efficient anti-reflection coating. Etching of the hole is then completed using a different etch which also removes the remaining photoresist, the silicon oxynitride as well as some of the titanium.

Abstract: A contactor system is adapted for use when testing a ball grid array (BGA) device, and includes a conductive socket that is retained on a testing board and that establishes a ground connection therewith. The socket is formed with a receiving space adapted for receiving the BGA device therein. An insulating guide unit is mounted on the socket in the receiving space and is adapted to guide loading movement of the BGA device into the receiving space via an open top section of the latter and to prevent undesired electrical contact between the socket and the BGA device. A surface mount matrix is disposed on top of the testing board and is clamped between the socket and the testing board. The surface mount matrix is accessible via an open bottom section of the receiving space, and is adapted to contact solder balls on the BGA device directly so as to establish electrical connection between the BGA device and testing circuit layout on the testing board.