Abstract: Disclosed is a detecting method of a wearable device, which comprises: providing a current to drive a light source to emit auxiliary light corresponding to ambient light received by the wearable device; and informing a wearing status indicative whether the wearable device is correctly worn by a user or not according to the current. By this way, the wearing status of the user can be easily detected.

Abstract: A semiconductor structure is provided. The semiconductor structure includes nanostructures over a substrate, a gate stack around the nanostructures, a gate spacer layer alongside the gate stack, an inner spacer layer between the gate spacer layer and the nanostructures, a source/drain feature adjoining the nanostructures, a contact plug over the source/drain feature, and a silicon germanium layer along the surface of the source/drain feature and between the contact plug and the inner spacer layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked nanostructure and a second stacked nanostructure extending above the isolation structure. The semiconductor device structure includes an inner spacer layer surrounding the first stacked nanostructure, and a dummy fin structure formed over the isolation structure. The dummy fin structure is between the first stacked nanostructure and the second stacked nanostructure, and a capping layer formed over the dummy fin structure. The inner spacer layer is in direct contact with the dummy fin structure and the capping layer.

Abstract: A memory device and a manufacturing method of the memory device are provided. The manufacturing method includes steps below. A plurality of stack structures including a tunneling dielectric layer and a floating gate are formed on a substrate. A liner material layer including a nitride liner layer is formed on the substrate. A top surface of the nitride liner layer is lower than a top surface of the floating gate and is higher than a top surface of the tunneling dielectric layer. An isolation material layer covering the liner material layer is formed on the substrate. The isolation material layer is oxidized, and a portion of the isolation material layer is removed to form an isolation structure. An inter-gate dielectric layer covering the stack structures and the isolation structure is formed on the substrate. A control gate covering the inter-gate dielectric layer is formed on the substrate.

Abstract: An antenna structure with wide radiation bandwidth in a reduced physical space includes a housing, a first feed portion, and a second feed portion. The housing includes a metallic side frame, a metallic middle frame, and a metallic back board. The metallic side frame defines a first gap and a second gap. The metallic back board defines a slot. The slot, the first and second gaps divide a first radiation portion and a second radiation from the metallic side frame. The first feed portion is electrically connected to the first radiation portion. The second feed portion is electrically connected to the second radiation portion. The metallic middle frame and the metallic back board are connected to each other to form a system ground plane to provide a ground for the antenna structure.

Abstract: An antenna structure with wide radiation bandwidth in a reduced physical space includes a housing, a first feed portion, and a second feed portion. The housing includes a metallic side frame, a metallic middle frame, and a metallic back board. The metallic side frame defines first and second gaps, and the metallic back board defines a slot. The slot, the first gap, and the second gap divide the metallic side frame to give a first radiation portion. The first and second feed portions are both electrically connected to the first radiation portion. When the first feed portion supplies a current, the current flows through the first radiation portion, toward the second gap to excite a first working mode. When the second feed portion supplies a current, the current flows through the first radiation portion, toward the first gap to excite a second working mode.

Abstract: A transferring chips method, including providing a plurality of chips on a first load-bearing structure; dividing the first load-bearing structure into a plurality of blocks, and each of the plurality of blocks including multiple chips of the plurality of chips; measuring a characteristic value of each of the plurality of chips; respectively calculating an average characteristic value of each of the plurality of blocks based on the characteristic values of the multiple chips of each of the plurality of blocks; and transferring the multiple chips of at least two blocks of the plurality of blocks with the average characteristic values within the same range to a second load-bearing structure.

Abstract: A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.

Abstract: A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.

Abstract: An integrated substrate for an anti-shake apparatus defined with an optical axis includes: a substrate, a lens module, an anti-shake apparatus and an image-sensing module. The substrate includes a frame having a predetermined thickness. The frame includes a first surface, a second surface, a first circuit layout, and a second circuit layout. The lens module is located above the substrate on the optical axis. The anti-shake apparatus is furnished between the lens module and the substrate. The image-sensing module has an active side and an inactive side, and the inactive side is furnished onto the second surface. The active side is located on the optical axis in a manner of facing the lens module. The anti-shake apparatus is coupled to the first circuit layout, while the image-sensing module is coupled to the second circuit layout. The first and second circuit layouts comprise a plurality of first and second metal leads, respectively.

Abstract: A semiconductor package includes a substrate having a first side and a second side opposite to the first side, a first type semiconductor die disposed on the first side of the substrate, a first compound attached to the first side and encapsulating the first type semiconductor die, and a second compound attached to the second side, causing a stress with respect to the first type semiconductor die in the first compound. A method for manufacturing the semiconductor package described herein is also disclosed.

Abstract: A HDMI apparatus is provided. The HDMI apparatus includes a first audio/video transceiver (A/V transceiver) configured to transmit an optical A/V signal to a second A/V transceiver; and a first sideband transceiver configured to drive a first laser diode to transmit a first optical sideband signal including a first control information or a first power information; wherein the first control information or the first power information is converted by a first Serializer/Deserializer (SERDES).

Abstract: An optical element driving mechanism having an optical axis includes a fixed portion, a movable portion, and a driving assembly. The movable portion is connected to the fixed portion. The driving assembly drives the movable portion to move in a direction that is parallel to the optical axis relative to the fixed portion, when viewed in the direction that is parallel to the optical axis, the optical element driving mechanism is a rectangular structure with a first side, a second side, a third side, and a fourth side, the first side and the third side are opposite, and the first side is adjacent to the second side and the fourth side.

Abstract: A loop antenna includes a printed circuit board (PCB), a first antenna structure and a second antenna structure. The PCB includes a first surface and a second surface relative to the first surface, and the PCB includes a clear region and a ground region, wherein the clear region is adjacent to the ground region. The first antenna structure is disposed in the clear region at the first surface. The first antenna structure includes a feed structure and a first ground end. The feed structure is coupled to a power feed end which is disposed in the ground region. The first ground end is coupled to the ground region. The second antenna structure is disposed relative to the first antenna structure at the second surface. The second antenna structure includes a second ground end. The second ground end is coupled to the ground region.

Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

Abstract: A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure.

Abstract: A wearable device includes: a sensing circuit and a processing circuit, wherein the sensing circuit is arranged to generate a wearing information output in each of a plurality of detecting periods, and the processing circuit is arranged to inform a wearing status indicative of a status of wearing the wearable device according to wearing information outputs generated in the plurality of detecting periods.