Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Abstract: A jig structure for assembling a high frequency connector includes a base on which a rotatable seat is provided, and the surface area of the rotatable seat is smaller than the base. A fixed table is provided on the rotatable seat. The fixed table further includes a first table, and an adjusting rod and a plurality of guide rods are provided on the first table. A plurality of assembly tables are provided on the adjusting rod and the guide rods. The assembly tables are correspondingly disposed, and their movement is controlled by the adjusting rod. A first assembly table and a second assembly table are provided on both sides of the fixed table. The first assembly table has movements along X-axis and Y-axis, and the second assembly stage has movements along Y-axis, thereby corresponding to the relative position of the assembly table and the fixed table so as to quickly place the circuit boards and connectors to be assemble.

Abstract: A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.

Abstract: A bandwidth allocation device includes a buffer device, a main scheduler, an oversubscription scheduler, a multiplexer and a detecting device. The buffer device is arranged to receive first data units from first ports and second data units from second ports and accordingly output these data units. The main scheduler is configured to schedule the first data units and accordingly output the first data units in sequence. The oversubscription scheduler is configured to schedule the second data units and accordingly output the second data units in sequence. The multiplexer is controlled by the main scheduler to select the first data units outputted by the main scheduler and the second data units outputted by the oversubscription scheduler for outputting. The detecting device is arranged to generate power-related information which the main scheduler relies on to control the multiplexer.

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

Abstract: A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack over a substrate. The substrate has a base and a first fin structure over the base, and the first gate stack wraps around a first upper portion of the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack. The method includes forming a first mask layer over a first sidewall of the first fin structure. The method includes forming a first stressor over a second sidewall of the first fin structure while the first mask layer covers the first sidewall. The first sidewall is opposite to the second sidewall. The method includes removing the first mask layer. The method includes forming a dielectric layer over the base and the first stressor. The dielectric layer covers the first sidewall.

Abstract: A floating connector includes a shell, a plurality of electrodes, two buckle members and a floating member. The shell has an accommodating space and a plurality of openings. The electrodes are disposed in the accommodating space and penetrate the openings to protrude from the openings. The buckle members are respectively disposed on two sides of the accommodating space. Each of the buckle members includes a fixed part, a contacting part, and an elastic part. The floating member includes a body, a plurality of electrode notches, and a bump. The electrode notches are formed on one side of the body that near the electrodes for receiving the electrodes protruding from the openings. The bump is disposed on the body and correspondingly to the notch, and the width of the bump is not greater than that of the notch, so that the bump is restricted in the notches by the guiding structure.

Abstract: A bandwidth allocation device includes a buffer device, a main scheduler, an oversubscription scheduler, a multiplexer and a detecting device. The buffer device is arranged to receive first data units from first ports and second data units from second ports and accordingly output these data units. The main scheduler is configured to schedule the first data units and accordingly output the first data units in sequence. The oversubscription scheduler is configured to schedule the second data units and accordingly output the second data units in sequence. The multiplexer is controlled by the main scheduler to select the first data units outputted by the main scheduler and the second data units outputted by the oversubscription scheduler for outputting. The detecting device is arranged to generate power-related information which the main scheduler relies on to control the multiplexer.

Abstract: Methods are proposed to define UE behavior for performing synchronization signal block (SSB) based radio link monitoring (RLM) and channel state information reference signal (CSI-RS) based RLM. In a first novel aspect, if CSI-RS based RLM-RS is not QCLed to any CORESET, then UE determines that CSI-RS RLM configuration is error and does not perform RLM accordingly. In a second novel aspect, SSB for RLM and RLM CSI-RS resources are configured with different numerologies. UE perform SSB based RLM and CSI-RS based RLM based on whether the SSB and CSI-RS resources are TDMed configured by the network. In a third novel aspect, when multiple SMTC configurations are configured to UE, UE determines an SMTC period and whether SMTC and RLM-RS are overlapped for the purpose of RLM evaluation period determination.

Abstract: A packet transmission control method used in a packet transmission circuit is provided that includes the steps outlined below. A packet receiving circuit, processing circuits and a packet sending circuit of the packet transmission circuit are kept in a non-operation status. The packet receiving circuit is woken up to the operation status to receive the packet stream and is restored to the non-operation status. The processing circuits are woken up to an operation status respectively according to an operation order thereof to receive, transmit and process the packet stream within a respective process time period and are restored to the non-operation status after the packet stream is processed. The packet sending circuit is woken up to the operation status to transmit the packet stream processed by the processing circuits to an external device and is restored to the non-operation status after the packet stream is transmitted.

Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm?3 and about 1020 cm?3.

Abstract: An electric table stand for simple assembly and adjustment includes a beam structure (10), support bars (20), and upright structures (30). Each of the support bars (20) includes a base (21) and a plurality of arms (211, 212, 213) extended from the base (21), wherein an accommodating space (A) is defined by the base (21) and the arms (211, 212, 213). One arm (213) of each of the support bars (20) supports one end of the beam structure (10), and the beam structure (10) is operatively moved in or out of the accommodating space (A). The upright structures (30) are connected to the support bars (20). Accordingly, it is easy to adjust and position each support bar (20) and each upright structure (30) on the beam structure (10).

Abstract: A method for detecting motion information includes the following steps. First, a pixel array is provided for detecting an image of a measured object located in a first distance range or in a second distance range, and the pixel array includes a plurality of invisible image sensing pixels and a plurality of visible image sensing pixels. Then, image detection is conducted within the first distance range by using the invisible image sensing pixels to output a plurality of invisible images. Next, the image detection is conducted within the second distance range by using the visible image sensing pixels to output a plurality of visible images. Then, the plurality of invisible images and the plurality of visible images are analyzed by using a processing unit, so as to obtain motion information of the measured object. A pixel array for detecting motion information and an image sensor are also provided.

Abstract: A method includes providing a structure having a substrate, first and second semiconductor fins extending from the substrate, and a dielectric fin between the first and second semiconductor fins; forming a temporary gate on top and sidewalls of the first and second semiconductor fins and the dielectric fin; forming gate spacers on sidewalls of the temporary gate; removing the temporary gate and a first portion of the dielectric fin between the gate spacers; forming a gate between the gate spacers and on top and sidewalls of the first and second semiconductor fins, wherein the dielectric fin is in physical contact with sidewalls of the gate; removing a second portion of the dielectric fin, thereby exposing the sidewalls of the gate; and performing an etching process to the gate through the exposed sidewalls of the gate, thereby separating the gate into a first gate segment and a second gate segment.

Abstract: A semiconductor device package includes a first substrate, a dielectric layer, a thin film transistor (TFT) and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The dielectric layer is disposed on the first surface of the first substrate. The dielectric layer has a first surface facing away from the first substrate and a second surface opposite to the first surface. The TFT layer is disposed on the dielectric layer. The electronic component is disposed on the second surface of the first substrate. A roughness of the first surface of the dielectric layer is less than a roughness of the first surface of the first substrate.

Abstract: A display device includes a substrate, a light-emitting element, and a transistor. The substrate has a top surface. The light-emitting element is disposed on the substrate, and includes a first electrode and a second electrode. The transistor is disposed on the substrate and electrically connected to the light-emitting element. The transistor includes a gate electrode and a semiconductor layer. The semiconductor layer includes an overlapping portion overlapped with the gate electrode. The first electrode and the second electrode of the light-emitting element do not overlap with the overlapping portion along a direction perpendicular to the top surface of the substrate.

Abstract: The invention discloses a connector with a direct locking structure. The connector comprises a male part and a female seat. The male part has a plurality of elastic parts, and each of the buckles is disposed on the outer sides of the plurality of the elastic parts. The female seat has a plurality of binding parts, and the binding parts respectively form two sides of the combining space, and the binding parts are correspondingly arranged to the buckles. The buckles are matched with the binding parts through deforming the elastic parts, so that the male parts and the female seats are further locked, wherein the locking of the male parts and the female seats are further released through deforming the elastic parts by the buckles and the binding parts.

Abstract: A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.