Abstract: A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height.

Abstract: A jig structure for assembling a high frequency connector includes a base on which a rotatable seat is provided, and the surface area of the rotatable seat is smaller than the base. A fixed table is provided on the rotatable seat. The fixed table further includes a first table, and an adjusting rod and a plurality of guide rods are provided on the first table. A plurality of assembly tables are provided on the adjusting rod and the guide rods. The assembly tables are correspondingly disposed, and their movement is controlled by the adjusting rod. A first assembly table and a second assembly table are provided on both sides of the fixed table. The first assembly table has movements along X-axis and Y-axis, and the second assembly stage has movements along Y-axis, thereby corresponding to the relative position of the assembly table and the fixed table so as to quickly place the circuit boards and connectors to be assemble.

Abstract: An antenna structure includes a housing, a first feed source, and a second feed source. The first feed source is electrically coupled to a first radiating portion of the housing and adapted to provide an electric current to the first radiating portion. The second feed source is electrically coupled to one of a second radiating portion or a third radiating portion of the housing. The other one of the second radiating portion or the third radiating portion is electrically coupled to the first radiating portion.

Abstract: A card connector includes a transmission conductor assembly. The transmission conductor assembly includes a first conductor group and a second conductor group. The first conductor group includes a backup transmission conductor, first and second signal transmission conductors, an inspection signal transmission conductor, first to seventh grounding transmission conductors, a command reset transmission conductor, first to sixth differential transmission conductors, first and second power transmission conductors, and a write-protection transmission conductor, each of which has two ends respectively forming a spring section and a soldering section. The second conductor group includes eighth to tenth grounding transmission conductors, seventh to tenth differential transmission conductors, and a third power transmission conductor each of which has two ends respectively forming a spring section and a soldering section.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.

Abstract: Ophthalmic compositions including compatible solute components and/or polyanionic components are useful in treating eyes, for example, to relieve dry eye syndrome, to protect the eyes against hypertonic insult and/or the adverse effects of cationic species on the ocular surfaces of eyes and/or to facilitate recovery from eye surgery.

Abstract: An integrated circuit includes a substrate, a dielectric layer over the substrate, a plurality of cells, a plurality of spacers and a plurality of conductive particles. Each of the cells includes a bottom portion in the dielectric layer and an upper portion protruding from the dielectric layer. The spacers are disposed over the dielectric layer and partially cover the upper portions of the cells, respectively. The spacers are disconnected from each other, and cover a first area of the dielectric layer and expose a second area of the dielectric layer. The conductive particles are disposed between the first area of the dielectric layer and the spacers.

Abstract: A semiconductor device package comprises a carrier, a stop layer, a barrier layer and an encapsulant. The carrier has a first surface and a second surface recessed with respect to the first surface. The stop layer is disposed on the second surface of the carrier. The barrier layer is disposed on the stop layer and protruded from the first surface of the carrier. The encapsulant is disposed on the first surface of the carrier. Further, the encapsulant has a side surface disposed on the barrier layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked structure and a second stacked structure extending above the isolation structure. The first stacked structure includes a plurality of first nanostructures stacked in a vertical direction, and the second stacked structure includes a plurality of second nanostructures stacked in the vertical direction. The semiconductor device structure also includes a first dummy fin structure formed over the isolation structure, and the first dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the first dummy fin structure, and a top surface of the capping layer is higher than a top surface of the first stacked structure and a top surface of the second stacked structure.

Abstract: FinFET device and method of forming the same are provided. The method of forming the FinFET device includes the following steps. A substrate having a plurality of fins is provided. An isolation structure is on the substrate surrounding lower portions of the fins. A hybrid fin is formed aside the fins and on the isolation structure. A plurality of gate lines and a dielectric layer are formed. The gate lines are across the fins and the hybrid fin, the dielectric layer is aside the gate lines. A portion of the gate lines is removed, so as to form first trenches in the dielectric layer and in the gate lines, exposing a portion of the hybrid fin and a portion of the fins underlying the portion of the gate lines. The portion of the fins exposed by the first trench and the substrate underlying thereof are removed, so as to form a second trench under the first trench. An insulating structure is formed in the first trench and the second trench.

Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the second waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, a removable media (e.g., a memory card, or a USB drive) may be configured to execute instructions with matrix operands and configured with: an interface to receive a video stream; and random access memory to buffer a portion of the video stream as an input to an Artificial Neural Network and to store instructions executable by the Deep Learning Accelerator and matrices of the Artificial Neural Network. Such a removable media can be used to replace an existing removable media used in a surveillance camera to record video or images. The Deep Learning Accelerator can execute the instructions to generate analytics of the buffer portion using the Artificial Neural Network, enabling the surveillance camera that is upgraded via the use of the removable media to provide intelligent services based on the analytics.

Abstract: A propulsion device with double-layer flow guiding assembly and a flight vehicle using the same are provided. The propulsion device includes a propulsion body, a first-layer flow guiding assembly and a second-layer flow guiding assembly. The propulsion body includes a housing, an airflow suction port and an airflow discharge port. The first-layer flow guiding assembly includes a front flow guiding ring and at least one first-layer flow guiding plate. The front flow guiding ring is disposed outside the airflow discharge port and has a first axis. The front flow guiding ring swings relative to the airflow discharge port along a first rotation axis. The first rotation axis intersects the first axis. The first-layer flow guiding plate is fixed in the front flow guiding ring and extends along the first rotation axis. The second-layer flow guiding assembly has a structure similar to the first-layer flow guiding assembly.

Abstract: A card connector includes a transmission conductor assembly. The transmission conductor assembly includes a first signal transmission conductor, a first power transmission conductor, an inspection signal transmission conductor, a second signal transmission conductor, a command reset transmission conductor, a first grounding transmission conductor, a second power transmission conductor, a first differential transmission conductor, a second differential transmission conductor, a third signal transmission conductor, a second grounding transmission conductor, a third grounding transmission conductor, a third differential transmission conductor, a fourth differential transmission conductor, a fourth grounding transmission conductor, a fifth grounding transmission conductor, a fifth differential transmission conductor, a sixth differential transmission conductor, and an outside grounding transmission conductor, each of which has a spring section and a soldering section.

Abstract: A card connector includes a transmission conductor assembly that includes a backup transmission conductor, a first signal transmission conductor, an inspection signal transmission conductor, a first grounding transmission conductor, a command reset transmission conductor, a first differential transmission conductor, a second differential transmission conductor, a second grounding transmission conductor, a third grounding transmission conductor, a fourth grounding transmission conductor, a first power transmission conductor, a second power transmission conductor, a third differential transmission conductor, a fourth differential transmission conductor, a second signal transmission conductor, a fifth grounding transmission conductor, a sixth grounding transmission conductor, a seventh grounding transmission conductor, a fifth differential transmission conductor, a sixth differential transmission conductor, and a write-protection transmission conductor, each of which has two ends respectively forming a spring se

Abstract: The application discloses a router coupled to a first device and a second device. The router includes a first packet input interface, a second packet input interface, a first register, a second register, a control circuit and a switch module. The switch module includes a control port, a first packet output interface and a second packet output interface. The application further discloses a routing method. The router and routing method saves idle time and improves quality of service.

Abstract: A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises alternately forming first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers include different materials and are stacked up along a direction substantially perpendicular to a top surface of the substrate; forming a dummy gate structure over the first and second semiconductor layers; forming a source/drain (S/D) trench along a sidewall of the dummy gate structure; forming inner spacers between edge portions of the first semiconductor layers, wherein the inner spacers are bended towards the second semiconductor layers; and epitaxially growing a S/D feature in the S/D trench, wherein the S/D feature contacts the first semiconductor layers and includes facets forming a recession away from the inner spacers.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a multilayer stack over the base. The semiconductor device structure includes a gate stack over the substrate and wrapping around the multilayer stack. The semiconductor device structure includes a dielectric layer over the base and covering a first sidewall of the multilayer stack. A first upper surface of the dielectric layer is lower than a second upper surface of the multilayer stack. The semiconductor device structure includes a stressor over a second sidewall of the multilayer stack. The first sidewall is opposite to the second sidewall.

Abstract: A semiconductor device package includes a display device, an electronic module and a conductive adhesion layer. The display device includes a first substrate and a TFT layer. The first substrate has a first surface and a second surface opposite to the first surface. The TFT layer is disposed on the first surface of the first substrate. The electronic module includes a second substrate and an electronic component. The second substrate has a first surface facing the second surface of the first substrate and a second surface opposite to the first surface. The electronic component is disposed on the second surface of the second substrate. The conductive adhesion layer is disposed between the first substrate and the second substrate.