Abstract: A HDMI apparatus is provided. The HDMI apparatus includes a first audio/video transceiver (A/V transceiver) configured to transmit an optical A/V signal to a second A/V transceiver; and a first sideband transceiver configured to drive a first laser diode to transmit a first optical sideband signal including a first control information or a first power information; wherein the first control information or the first power information is converted by a first Serializer/Deserializer (SERDES).

Abstract: A semiconductor structure is provided. The semiconductor structure includes nanostructures over a substrate, a gate stack around the nanostructures, a gate spacer layer alongside the gate stack, an inner spacer layer between the gate spacer layer and the nanostructures, a source/drain feature adjoining the nanostructures, a contact plug over the source/drain feature, and a silicon germanium layer along the surface of the source/drain feature and between the contact plug and the inner spacer layer.

Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT. The DUT includes an antenna and radiates a RF signal. The test kit further includes a reflector having a lower surface. The RF signal emitted from the antenna of the DUT is reflected by the reflector and a reflected RF signal is received by the antenna of the DUT.

Abstract: Methods of fabricating optical devices with high refractive index materials are disclosed. The method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. A material of the patterned template layer has a first refractive index. The method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. The waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.

Abstract: An optical element driving mechanism is provided that includes a fixed assembly, a movable assembly, a driving assembly, and a circuit assembly. The movable assembly is configured to be connected to an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable member to move relative to the fixed assembly. The circuit assembly is electrically connected to the driving assembly, and the circuit assembly includes an electrical connection element having a resin material.

Abstract: A mixer for mixing and degassing fluids includes a revolution device having a revolution base to be driven for rotation; a first spin device connected to the revolution base of the revolution device; a first barrel connected to the first spin device to be spun by the first spin device; an transmitting coil electrically connected to a power source to generate a time-vary magnetic field; and a receiving coil connected to the revolution base of the revolution device and electrically connected to the first spin device, wherein the receiving coil rotates with the revolution base. The receiving coil receives the power from the time-vary magnetic field of the transmitting coil and produces an electromotive force to be supplied to the first spin device.

Abstract: An integrated circuit chip includes a core circuit, a first bond pad, a first switch circuit, a second configuration resistor, a control circuit, and a storage unit. The first bonding pad is coupled to a first external reference voltage through a first node, and the first node is coupled to the first external reference voltage through a bonding wire or a first configuration resistor. The first switch circuit is coupled between a first internal reference voltage and the first node. The second configuration resistor is coupled between the first internal reference voltage and the first switch circuit or between the first switch circuit and the first node. In a first mode, the control circuit turns on the first switch circuit, and writes a configuration state of the first bonding pad to the storage unit. In a second mode, the control circuit turns off the first switch circuit.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor strip over a substrate. The semiconductor strip includes a first semiconductor stack and a second semiconductor stack over the first semiconductor stack. A dummy gate stack is formed to cross the semiconductor strip. The dummy gate stack is replaced with a first metal gate stack and a second metal gate stack. The first metal gate stack is in contact with the first semiconductor layer of the first semiconductor stack and the second metal gate stack is in contact with the first semiconductor layer of the second semiconductor stack.

Abstract: A semiconductor device package includes a first substrate, a second substrate, a conductive structure, a first solder and a second solder. The second substrate is disposed over the first substrate. The conductive structure is disposed between the first substrate and the second substrate. The conductive structure includes a first wetting portion, a second wetting portion, and a non-wetting portion disposed between the first wetting portion and the second wetting portion. The first solder covers the first wetting portion and connects the conductive structure to the first substrate. The second solder covers the second wetting portion and connects the conductive structure to the second substrate. The first solder is spaced apart from the second solder by the non-wetting portion.

Abstract: An embodiment is a method of manufacturing a semiconductor device. The method includes forming a fin on a substrate. A gate structure is formed over the fin. A recess is formed in the fin proximate the gate structure. A gradient doped region is formed in the fin with a p-type dopant. The gradient doped region extends from a bottom surface of the recess to a vertical depth below the recess in the fin. A source/drain region is formed in the recess and on the gradient doped regions.

Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

Abstract: An integrated substrate for an anti-shake apparatus defined with an optical axis includes: a substrate, a lens module, an anti-shake apparatus and an image-sensing module. The substrate includes a frame having, a predetermined thickness. The frame includes a first surface, a second surface, a first circuit layout, and a second circuit layout. The lens module is located above the substrate on the optical axis. The anti-shake apparatus is furnished between the lens module and the substrate. The image-sensing module has an active side and an inactive side, and the inactive side is furnished onto the second surface. The active side is located on the optical axis in a manner of facing the lens module. The anti-shake apparatus is coupled to the first circuit layout, while the image-sensing module is coupled to the second circuit layout. The first and second circuit layouts comprise a plurality of first and second metal leads, respectively.

Abstract: A method includes forming an active fin using a hard mask as an etching mask, wherein the active fin comprises a source region, a drain region, and a channel region, the hard mask remains over the active fin after etching the semiconductive substrate, and the hard mask has a first portion vertically overlapping the source region of the active fin, a second portion vertically overlapping the channel region of the active fin, and a third portion vertically overlapping the drain region of the active fin. A sacrificial gate is formed over the second portion of the hard mask and the channel region of the active fin. The first and third portions of the hard mask are etched. After etching the first and third portions of the hard mask, a gate spacer is formed extending along sidewalls of the sacrificial gate, and the sacrificial gate is replaced with a replacement gate.

Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.

Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.

Abstract: A portable electronic device is provided. The portable electronic device includes a body, an image sensor and a main system. The image sensor continually captures a first image outside the body, detects at least one motion of a user according to the first image, and generates a control signal related to the motion. The main system receives the control signal from the image sensor and executes a function or a service corresponding to the motion according to the control signal.

Abstract: A headset controller takes a first touch sensor, a second touch sensor, a first pressure sensor, and a second pressure sensor as a control medium for users. The headset controller can generate four different output instructions by the users touching or pressing the operating interface. The headset controller integrates various sensing methods to generate the needed output instructions.

Abstract: A smart motion detection device includes an image sensor, an infrared sensor and a processor. The image sensor captures a monitoring image. The infrared sensor detects a thermal motion condition and provides an alarm signal accordingly. The processor executes an image recording mode of the image sensor only according to the alarm signal when an image quality of the monitoring image is unacceptable.

Abstract: A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.