Patents by Inventor Changging LIN

Changging LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including a FinFET structure and method for fabricating the same
    Patent number: 12087636
    Abstract: The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Shi Ning Ju, Chih-Hao Wang, Kuan-Ting Pan
  • Semiconductor package device and method of manufacturing the same
    Patent number: 12087652
    Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: September 10, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi Chen, Chang-Lin Yeh, Jen-Chieh Kao
  • Semiconductor device package and method of manufacturing the same
    Patent number: 12089349
    Abstract: A semiconductor device package includes a display device, an encapsulation layer disposed in direct contact with the display device, and a reinforced structure surrounded by the encapsulation layer. The reinforced structure is spaced apart from a surface of the display device. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: September 10, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Hung Chen, Yung I Yeh, Chang-Lin Yeh, Sheng-Yu Chen
  • Semiconductor device structure and method for forming the same
    Patent number: 12087768
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures stacked in a vertical direction over a substrate, and a first dummy fin structure between the first nanostructures and the second nanostructures. The semiconductor device structure includes a first gate structure formed over the first nanostructures, wherein the first gate structure includes a gate dielectric layer, and the gate dielectric layer is in direct contact with a sidewall surface of the first dummy fin structure.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Chiang, Shi-Ning Ju, Chih-Hao Wang, Kuan-Ting Pan, Zhi-Chang Lin
  • Transistor, semiconductor structure, and manufacturing method thereof
    Patent number: 12080768
    Abstract: A transistor includes a gate electrode, a gate dielectric layer covering the gate electrode, an active layer covering the gate dielectric layer and including a first metal oxide material, and source/drain electrodes disposed on the active layer and made of a second metal oxide material with an electron concentration of at least about 1018 cm?3. A semiconductor structure and a manufacturing method are also provided.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: September 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chuang, Chang-Lin Yang, Katherine H. Chiang, Mauricio Manfrini
  • Semiconductor structure and method for forming the same
    Patent number: 12074204
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes a protection layer and alternating first and second semiconductor layers over the protection layer. The method also includes etching the fin structure to form a source/drain recess, forming a sacrificial contact in the source/drain recess, forming a source/drain feature over the sacrificial contact in the source/drain recess, removing the first semiconductor layers of the fin structure, thereby forming a plurality of nanostructures, forming a gate stack wrapping around the nanostructures, removing the substrate thereby exposing the protection layer and the sacrificial contact and replacing the sacrificial contact with a contact plug.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Hung Chang, Lo Heng Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien-Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Antenna structure and wireless communication device using same
    Patent number: 12068527
    Abstract: An antenna structure with wide radiation bandwidth in a reduced physical space includes a housing, a first feed portion, and a second feed portion. The housing includes a metallic side frame, a metallic middle frame, and a metallic back board. The metallic side frame defines first and second gaps, and the metallic back board defines a slot. The slot, the first gap, and the second gap divide the metallic side frame to give a first radiation portion. The first and second feed portions are both electrically connected to the first radiation portion. When the first feed portion supplies a current, the current flows through the first radiation portion, toward the second gap to excite a first working mode. When the second feed portion supplies a current, the current flows through the first radiation portion, toward the first gap to excite a second working mode.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: August 20, 2024
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Cho-Kang Hsu, Min-Hui Ho, Te-Chang Lin
  • Latch-up prevention
    Patent number: 12062721
    Abstract: A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chen, Kuo-Cheng Chiang, Zhi-Chang Lin
  • METHOD FOR FORMING LONG CHANNEL BACK-SIDE POWER RAIL DEVICE
    Publication number: 20240266223
    Abstract: A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.
    Type: Application
    Filed: February 13, 2024
    Publication date: August 8, 2024
    Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang, Zhi-Chang Lin, Li-Zhen Yu
  • OPTICAL ELEMENT DRIVING MECHANISM
    Publication number: 20240264405
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Application
    Filed: April 16, 2024
    Publication date: August 8, 2024
    Inventors: Chao-Chang HU, Liang-Ting HO, Chen-Er HSU, Yi-Liang CHAN, Fu-Lai TSENG, Fu-Yuan WU, Chen-Chi KUO, Ying-Jen WANG, Wei-Han HSIA, Yi-Hsin TSENG, Wen-Chang LIN, Chun-Chia LIAO, Shou-Jen LIU, Chao-Chun CHANG, Yi-Chieh LIN, Shang-Yu HSU, Yu-Huai LIAO, Shih-Wei HUNG, Sin-Hong LIN, Kun-Shih LIN, Yu-Cheng LIN, Wen-Yen HUANG, Wei-Jhe SHEN, Chih-Shiang WU, Sin-Jhong SONG, Che-Hsiang CHIU, Sheng-Chang LIN
  • Chip transferring method and the apparatus thereof
    Patent number: 12057337
    Abstract: A chip transferring method includes providing a plurality of chips on a first load-bearing structure; measuring photoelectric characteristic values of the plurality of chips; categorizing the plurality of chips into a first portion chips and a second portion chips according to the photoelectric characteristic values of the plurality of chips, wherein the second portion chips comprise parts of the plurality of chips which photoelectric characteristic value falls within an unqualified range; removing the second portion chips from the first load-bearing structure; dividing the first portion chips into a plurality of blocks according to the photoelectric characteristic values, and each of the plurality of blocks comprising multiple chips of the first portion chips; and transferring the multiple chips of one of the plurality of blocks to a second load-bearing structure.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: August 6, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, De-Shan Kuo, Chang-Lin Lee, Jhih-Yong Yang
  • METHOD OF PROCESSING LIGHT-EMITTING ELEMENTS, SYSTEM AND DEVICE USING THE SAME
    Publication number: 20240258455
    Abstract: A method of processing light-emitting elements includes: placing a plurality of LED dies from original wafers or trays on each trays of a next-stage carrier, based on a predetermined pattern. The predetermined pattern arranges two adjacent LED groups in a first direction on the original wafer or trays to be placed on two non-adjacent positions in the first direction on the tray of the next-stage carrier. The LED dies on the original wafer or trays have a first horizontal pitch and a first vertical pitch. The LED dies on each tray of the next-stage carrier have a second horizontal pitch and a second vertical pitch. The second horizontal pitch is greater than the first horizontal pitch, or the second vertical pitch is greater than the first vertical pitch. Besides, a light-emitting element device using the aforementioned method is also provided.
    Type: Application
    Filed: April 16, 2024
    Publication date: August 1, 2024
    Applicant: EPISTAR CORPORATION
    Inventors: Min-Hsun HSIEH, Chang-Lin LEE
  • Field effect transistor with inner spacer liner layer and method
    Patent number: 12051736
    Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Chuang, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Method for manufacturing semiconductor structure with isolation strips
    Patent number: 12051693
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a plurality of fin structures extending along a first direction over a substrate, forming a low-k isolation strip over the substrate, the low-k isolation strip extending along the first direction and between the plurality of fin structures; and forming a high-k isolation strip on top of the low-k isolation strip.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shi Ning Ju, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang, Kuan-Ting Pan, Zhi-Chang Lin
  • Electric push rod with dual brake mechanism
    Patent number: 12049933
    Abstract: An electric push rod with a dual brake mechanism includes an electric motor, a transmission device, a first brake mechanism and a second brake mechanism. The electric motor has a driving wheel. The transmission device is installed on a side of the electric motor and includes a deceleration mechanism, a lead screw, a driven wheel, and a telescopic pipe. The deceleration mechanism is disposed between the driving wheel and the driven wheel. The lead screw is sheathed with the driven wheel and the driven wheel is driven by the electric motor to rotate together with the lead screw. The telescopic pipe and the lead screw are screwed and driven. The lead screw is sheathed with the first brake mechanism formed on a side edge of the driven wheel. The lead screw is sheathed with the second brake mechanism disposed between the driven wheel and the telescopic pipe.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: July 30, 2024
    Assignee: TIMOTION TECHNOLOGY CO., LTD.
    Inventor: Yu-Chang Lin
  • MANUFACTURING METHOD OF ELECTRONIC DEVICE
    Publication number: 20240250219
    Abstract: A manufacturing method of an electronic device includes: providing a first substrate, which has a base layer and a plurality of electronic components disposed on the base layer; adhering adhesive material to each of the plurality of electronic components; providing a target substrate, wherein the target substrate and the first substrate are separated from each other by a distance; and transferring at least part of the plurality of electronic components adhered with the adhesive material to the target substrate through a laser process, wherein at least part of the plurality of electronic components are attached to the target substrate via the adhesive material.
    Type: Application
    Filed: January 3, 2024
    Publication date: July 25, 2024
    Inventors: Kai CHENG, Fang-Ying LIN, Ming-Chang LIN, Tsau-Hua HSIEH
  • LIGHT-EMITTING DEVICE
    Publication number: 20240249983
    Abstract: A light-emitting device includes a substrate, a light-emitting diode, a first layer, a color filter layer, and a second layer. The light-emitting diode is disposed on the substrate. The first layer is disposed on the substrate and has an opening. At least a portion of the light-emitting diode is disposed in the opening of the first layer. The color filter layer is disposed on the light-emitting diode. The second layer is disposed on the first layer and has an opening overlapped with the opening of the first layer. The second layer is configured to shield light emitted from the light-emitting diode. In the cross-sectional view of the light-emitting device, the minimum width of the opening of the first layer is less than the minimum width of the opening of the second layer.
    Type: Application
    Filed: April 2, 2024
    Publication date: July 25, 2024
    Inventors: Tung-Kai LIU, Tsau-Hua HSIEH, Wei-Cheng CHU, Chun-Hsien LIN, Chandra LIUS, Ting-Kai HUNG, Kuan-Feng LEE, Ming-Chang LIN, Tzu-Min YAN, Hui-Chieh WANG
  • Method of fabricating magneto-resistive random access memory (MRAM)
    Patent number: 12048250
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells by chemical reaction. The metal components are then removed by chemical reaction.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin Yang, Chung-Te Lin, Sheng-Yuan Chang, Han-Ting Lin, Chien-Hua Huang
  • SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    Publication number: 20240243004
    Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A first trench isolation structure is disposed in the substrate between the first device region and the second device region. The first trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is lower than the second bottom surface. The first trench isolation structure includes a first top surface within the first device region and a second top surface within the second device region. The first top surface is coplanar with the second top surface.
    Type: Application
    Filed: February 13, 2023
    Publication date: July 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ling Wang, Ping-Hung Chiang, Ta-Wei Chiu, Chia-Wen Lu, Wei-Lun Huang, Yueh-Chang Lin
  • ID patch
    Patent number: D1036863
    Type: Grant
    Filed: January 11, 2024
    Date of Patent: July 30, 2024
    Assignee: TUMI, INC.
    Inventors: Pablo Chao, Peter Chang-Lin Wu, Victor G. Sanz