Patents by Inventor Changging LIN

Changging LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379446
    Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240379670
    Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.
    Type: Application
    Filed: June 6, 2023
    Publication date: November 14, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Ting Hu, Chih-Yi Wang, Yao-Jhan Wang, Wei-Che Chen, Kun-Szu Tseng, Yun-Yang He, Wen-Liang Huang, Lung-En Kuo, Po-Tsang Chen, Po-Chang Lin, Ying-Hsien Chen
  • Patent number: 12144113
    Abstract: A circuit board structure includes a substrate, a first build-up structure layer, first and second external circuit layers, at least one first conductive via, and second conductive vias. The first build-up structure layer is disposed on a first circuit layer of the substrate. The first external circuit layer is disposed on the first build-up structure layer. The second external circuit layer is disposed on a second circuit layer and a portion of a third dielectric layer of the substrate. The first conductive via is electrically connected to the first external circuit layer and the second external circuit layer to define a signal path. The second conductive vias surround the first conductive via, and the first external circuit layer, the second conductive vias, the first circuit layer, the outer conductive layer, and the second external circuit layer define a first ground path. The first ground path surrounds the signal path.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: November 12, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Chih-Chiang Lu, Chi-Min Chang, Ming-Hao Wu, Yi-Pin Lin, Tung-Chang Lin, Jun-Rui Huang
  • Publication number: 20240371953
    Abstract: A transistor includes a gate electrode, a gate dielectric layer covering the gate electrode, an active layer covering the gate dielectric layer and including a first metal oxide material, and source/drain electrodes disposed on the active layer and made of a second metal oxide material with an electron concentration of at least about 1018 cm?3. A semiconductor structure and a manufacturing method are also provided.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chuang, Chang-Lin Yang, Katherine H. CHIANG, Mauricio MANFRINI
  • Publication number: 20240371866
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures stacked in a vertical direction over a substrate, and a first dielectric structure between the first nanostructures and the second nanostructures. The semiconductor device structure includes a first gate structure formed over the first nanostructures. The first gate structure comprises a gate dielectric layer, and a topmost surface of the gate dielectric layer is higher than a top surface of the first dielectric structure.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng CHIANG, Shi-Ning JU, Chih-Hao WANG, Kuan-Ting PAN, Zhi-Chang LIN
  • Publication number: 20240364264
    Abstract: Aspects of this disclosure relate to a frequency multiplier with a transmission line in an input matching network. The frequency multiplier can multiply a frequency of a radio frequency input signal. The transmission line can provide a second harmonic trap. The transmission line can be electrically connected between input terminals of a pair of balanced transistors of the frequency multiplier.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventor: Hsin-Chang Lin
  • Publication number: 20240363759
    Abstract: A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Shih-Cheng Chen, Kuo-Cheng Chiang, Zhi-Chang Lin
  • Publication number: 20240364052
    Abstract: A connector assembly comprises a wire end connector, a board end connector, and an operating element. The board end connector includes a base and an extending tube body, which laterally forms a protrusion. The wire end connector includes a body and a wire connecting portion. The body has a shell that forms a guide groove and a side hole. The operating element has a pivot portion, a first extending arm, and a second extending arm. When the board end connector and the wire end connector are in an initial state and the operating element is in an unlocked position, the second extending arm is away from the guide groove. When the board end connector and the wire end connector are switched to a mating state, the protrusion contacts the first extending arm, causing the operating element to rotate from the unlocked position to a locked position.
    Type: Application
    Filed: November 20, 2023
    Publication date: October 31, 2024
    Inventors: Hsien-Chang LIN, Chun-Wei CHANG
  • Publication number: 20240358148
    Abstract: A an electric deck frame structure (1, 1A) includes: corner lifting vertical posts (10), each having a carrying seat (11) and a retractable rod (12), the carrying seat includes a first connection part (111) having a first electric connection assembly (1133) and a second connection part (116) having a second electric connection assembly (1183); connection pipes (20), connected to the corner lifting vertical posts (10) and having a first opening (21) and a second opening (22); a transformer (30) having an electricity input port (31) arranged corresponding to the first opening (21) and an electricity output port (32) arranged corresponding to the second opening (22), the transformer is hidden in the connection pipe, and a power and signal main cable (40), connected to the electricity output port (32), the first electric connection assembly (1133) and the second electric connection assembly (1183).
    Type: Application
    Filed: July 19, 2023
    Publication date: October 31, 2024
    Inventor: Yu-Chang LIN
  • Publication number: 20240363703
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures, a gate stack surrounding the nanostructures, a first source/drain feature and a second source/drain feature adjoining a first side and a second side of the plurality of nanostructures, respectively, a first contact plug under and electrically connected to the first source/drain feature, a second contact plug over and electrically connected to the second source/drain feature, and an insulating layer surrounding the second contact plug and covering a top surface of the first source/drain feature.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hung CHANG, Lo Heng CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien-Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240359072
    Abstract: A golf bag strap support system includes a central hub having a hub body and two articulated strap connectors secured to the hub body. The system further includes two support straps, with each support strap having a first end and a second end. The system further includes two shoulder straps, with each shoulder strap having a first end and a second end. Each of the first ends of the support strap and the shoulder strap is secured to the golf bag. Each second end of the support strap is secured to the hub body (34) of the central portion. Each second end of the shoulder strap is secured to a strap connector of the two articulated strap connectors of the central hub. The two support straps and the two shoulder straps are configured with respect to the central hub in a generally X-shaped configuration.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Peter Chang-Lin Wu, Victor G. Sanz
  • Publication number: 20240359071
    Abstract: A device for use with a golf bag includes a loop including a first end, two sides and a second end, which is opposite the first end. The device further includes a movable gate provided on one side of the loop. The movable gate is movable from a biased closed position to an open position. The device further includes a cross member dividing the loop into a first loop and a second loop. The first loop is defined by the cross member, the sides and the first end and the second loop is defined by the cross member, the sides and the second end. The cross member includes a lip configured to function as a bottle opener with the second end. The first loop is configured to receive an item.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Peter Chang-Lin Wu, Victor G. Sanz
  • Patent number: 12127680
    Abstract: Provided are an air cell device and an air mattress system thereof. The air cell device includes an air cell which has therein an upper connection segment and a lower connection segment. The upper connection segment and the lower connection segment each have a curved portion whereby the air cell is partitioned to become a multilayered air cell so as to mitigate air cell bending or air cell inversion, thereby improving the lying human being's comfort.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: October 29, 2024
    Assignee: WELLELL INC.
    Inventors: Chih-Kuang Chang, Sheng-Wei Lin, Chin-Chang Lin, Yue-Yin Chao, Yu-Hao Chen
  • Publication number: 20240355818
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Zhi-Chang Lin, Huan-Chieh Su, Kuo-Cheng Chiang
  • Publication number: 20240355901
    Abstract: A method for forming a semiconductor device structure includes forming a fin structure, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers. The method includes forming an epitaxial structure in the recess.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hung CHANG, Shih-Cheng CHEN, Chih-Hao WANG, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Zhi-Chang LIN, Chien-Ning YAO, Tsung-Han CHUANG
  • Publication number: 20240355908
    Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Tsung-Han CHUANG, Zhi-Chang LIN, Shih-Cheng CHEN, Jung-Hung CHANG, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240347535
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate fin and a second substrate fin extending in a first direction, a first isolation strip extending in the first direction and spaced apart from the first substrate fin and the second substrate fin, a first source/drain structure on the first substrate fin, and a second source/drain structure on the second substrate fin. The first isolation strip is sandwiched between and in contact with a first sidewall of the first source/drain structure and a first sidewall of the second source/drain structure.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Chih-Hao WANG, Kuan-Ting PAN, Zhi-Chang LIN
  • Publication number: 20240348123
    Abstract: A linear actuator includes an actuating mechanism, a telescopic structure and a hand rotary releasing structure. The hand rotary releasing structure includes a connecting seat, a clutch seat, a clutch, an adaptor sleeve and a return spring. A peripheral surface of the connecting seat is disposed with multiple clutch troughs. The clutch seat includes multiple engaging troughs. The clutch is disposed between the connecting seat and the clutch seat. The adaptor sleeve is disposed around the clutch and includes multiple spiral troughs. The return spring is disposed around the connecting seat and abuts against the clutch to reduce the activating time and steps of release.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 17, 2024
    Inventor: Yu-Chang LIN
  • Publication number: 20240349616
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells by chemical reaction. The metal components are then removed by chemical reaction.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin YANG, Chung-Te LIN, Sheng-Yuan CHANG, Han-Ting LIN, Chien-Hua HUANG
  • Patent number: D1048933
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: October 29, 2024
    Inventor: Yao-Chang Lin