Patents by Inventor Chao-Hsiung Wang
Chao-Hsiung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150091099Abstract: A method includes forming a semiconductor fin, forming a dummy gate on a top surface and sidewalls of the semiconductor fin, and removing the dummy gate to form a recess. The semiconductor fin is exposed to the recess. After the dummy gate is removed, an oxidation is performed on the semiconductor fin to form a condensed germanium-containing fin in the recess, and a silicon oxide layer on a top surface and sidewalls of the condensed germanium-containing fin. The method further includes forming a gate dielectric over the condensed germanium-containing fin, and forming a gate electrode over the gate dielectric.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Zhiqiang Wu, Jiun-Jia Huang, Chao-Hsiung Wang, Chi-Wen Liu
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Patent number: 8981496Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards, forming a fin, a gate dielectric over a top surface and sidewalls of the fin, a liner overlaying the gate dielectric, and an uninterrupted metallic feature over the liner a portion of the liner overlaying the gate dielectric, wherein the liner extends from a top surface of the uninterrupted metallic feature and covers sidewalls of the metallic feature, and wherein the gate dielectric, liner, and uninterrupted metallic feature collectively form a gate, a gate contact barrier, and a gate contact.Type: GrantFiled: February 27, 2013Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Wen Liu, Chao-Hsiung Wang
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Publication number: 20150069474Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material, wherein a bottom portion of the upper portion comprises a dopant with a first peak concentration; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and an isolation structure surrounding the fin structure, wherein a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.Type: ApplicationFiled: September 11, 2013Publication date: March 12, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao Hsiung Wang, Chi-Wen Liu
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Publication number: 20150054039Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the FinFET device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate. A plurality of three-dimensional fins protrude from a top surface of the semiconductor substrate at locations between the plurality of isolation regions. Respective three-dimensional fins have an epitaxial enhancement structure that introduces a strain into the three-dimensional fin. The epitaxial enhancement structures are disposed over a semiconductor material within the three-dimensional fin at a position that is more than 10 nanometers above a bottom of an adjacent isolation region. Forming the epitaxial enhancement structure at such a position provides for sufficient structural support to avoid isolation region collapse.Type: ApplicationFiled: August 20, 2013Publication date: February 26, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Chao Hsiung Wang, Chi-Wen Liu
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Publication number: 20150035020Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. For example, a substrate including a first region and a second region is provided. One or more first semiconductor device structures are formed on the first region. One or more semiconductor fins are formed on the second region. One or more second semiconductor device structures are formed on the semiconductor fins. A top surface of the semiconductor fins is higher than a top surface of the first semiconductor device structures.Type: ApplicationFiled: August 1, 2013Publication date: February 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHI-WEN Liu, CHAO-HSIUNG WANG
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Publication number: 20140264289Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang, Ming Zhu
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Publication number: 20140252442Abstract: The present disclosure provides one embodiment of a method of forming a tunnel field effect transistor (TFET). The method includes forming a semiconductor mesa on a semiconductor substrate; performing a first implantation to the semiconductor substrate and the semiconductor mesa to form a drain of a first type conductivity; forming a first dielectric layer on the semiconductor substrate and sidewall of the semiconductor mesa; forming a gate stack on the sidewall of the semiconductor mesa and the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the gate stack; and forming, on the semiconductor mesa, a source having a second type conductivity opposite to the first type conductivity. The gate stack includes a gate dielectric and a gate electrode on the gate dielectric. The source, drain and gate stack are configured to form the TFET.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Inventors: Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang, Ming Zhu
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Patent number: 8828823Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins.Type: GrantFiled: April 2, 2014Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Wen Liu, Chao-Hsiung Wang
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Publication number: 20140239396Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards, forming a fin, a gate dielectric over a top surface and sidewalls of the fin, a liner overlaying the gate dielectric, and an uninterrupted metallic feature over the liner a portion of the liner overlaying the gate dielectric, wherein the liner extends from a top surface of the uninterrupted metallic feature and covers sidewalls of the metallic feature, and wherein the gate dielectric, liner, and uninterrupted metallic feature collectively form a gate, a gate contact barrier, and a gate contact.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Wen Liu, Chao-Hsiung Wang
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Publication number: 20140206166Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins.Type: ApplicationFiled: April 2, 2014Publication date: July 24, 2014Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chi-Wen Liu, Chao-Hsiung Wang
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Publication number: 20140206156Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.Type: ApplicationFiled: April 2, 2014Publication date: July 24, 2014Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chi-Wen Liu, Chao-Hsiung Wang
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Publication number: 20140197458Abstract: An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.Type: ApplicationFiled: September 3, 2013Publication date: July 17, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Jiun-Jia Huang, Chao-Hsiung Wang, Chi-Wen Liu
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Patent number: 8723236Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins.Type: GrantFiled: October 13, 2011Date of Patent: May 13, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Wen Liu, Chao-Hsiung Wang
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Patent number: 8723272Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.Type: GrantFiled: October 4, 2011Date of Patent: May 13, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Wen Liu, Chao-Hsiung Wang
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Publication number: 20140117454Abstract: An embodiment fin field effect transistor (FinFET) device includes fins formed from a semiconductor substrate, a non-recessed shallow trench isolation (STI) region disposed between the fins, and a dummy gate disposed on the non-recessed STI region.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Wen Liu, Chao-Hsiung Wang
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Publication number: 20140065740Abstract: A photonic device generates light from a full spectrum of lights including white light. The device includes two or more LEDs grown on a substrate, each generating light of a different wavelength and separately controlled. A light-emitting structure is formed on the substrate and apportioned into the two or more LEDs by etching to separate the light-emitting structure into different portions. At least one of the LEDs is coated with a phosphor material so that different wavelengths of light are generated by the LEDs while the same wavelength of light is emitted from the light-emitting structure.Type: ApplicationFiled: November 20, 2013Publication date: March 6, 2014Applicant: TSMC Solid State Lighting Ltd.Inventors: Hsin-Chieh Huang, Chao-Hsiung Wang
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Patent number: 8604498Abstract: A photonic device generates light from a full spectrum of lights including white light. The device includes two or more LEDs grown on a substrate, each generating light of a different wavelength and separately controlled. A light-emitting structure is formed on the substrate and apportioned into the two or more LEDs by etching to separate the light-emitting structure into different portions. At least one of the LEDs is coated with a phosphor material so that different wavelengths of light are generated by the LEDs while the same wavelength of light is emitted from the light-emitting structure.Type: GrantFiled: March 26, 2010Date of Patent: December 10, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Hsin-Chieh Huang, Chao-Hsiung Wang
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Patent number: 8564018Abstract: A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.Type: GrantFiled: February 27, 2008Date of Patent: October 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Chich Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang, Chenming Hu, Fu-Liang Yang, Shih-Chang Chen, Mong-Song Liang, Liang-Gi Yao
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Patent number: RE45165Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.Type: GrantFiled: February 14, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yu Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang
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Patent number: RE45180Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.Type: GrantFiled: June 2, 2010Date of Patent: October 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang