Patents by Inventor Chao Zhang

Chao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7723374
    Abstract: Compounds are described that are active on PPARs, including pan-active compounds. Also described are methods for developing or identifying compounds having a desired selectivity profile.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: May 25, 2010
    Assignee: Plexxikon, Inc.
    Inventors: Dean R. Artis, Prabha N. Ibrahim, Jack Lin, Chao Zhang
  • Patent number: 7702178
    Abstract: A method and apparatus for reducing noise in at least one frame in an image sequence is disclosed. A minimum function is applied to the at least one frame to produce a plurality of minimum values. A mask is generated in accordance with the plurality of minimum values. The mask is applied to reduce the noise in the at least one frame. In one embodiment, impulse noise is reduced. In another embodiment wideband non-linear noise is reduced.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: April 20, 2010
    Assignee: Sarnoff Corporation
    Inventors: James Bergen, Chao Zhang, Gooitzen Van Der Wal
  • Patent number: 7691739
    Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: April 6, 2010
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
  • Patent number: 7687506
    Abstract: Inhibition of protein kinases having one or more cysteine residues within the ATP binding site is effected by contacting the kinase, per se or in a cell or subject, with an inhibitory-effective amount of a compound having a heterocyclic core structure comprised of two or more fused rings containing at least one nitrogen ring atom, and an electrophilic substituent that is capable of reacting with a cysteine residue within the ATP binding site of a kinase. Preferred compounds include certain pyrrolopyrimidines and oxindoles having such an electrophilic substituent and optionally an aromatic or heteroaromatic substituent that is capable of interacting with a threonine or smaller residue located in the gatekeeper position of the kinase. Kinases lacking such cysteine residues may be engineered or modified so that they are capable of being inhibited by such compounds by replacing a valine or other amino acid residue within the ATP binding site by a cysteine residue.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: March 30, 2010
    Assignee: The Regents of the University of California
    Inventors: Jack Taunton, Michael Cohen, Kevan Shokat, Chao Zhang
  • Patent number: 7678586
    Abstract: An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor structure. We cure the film by exposing the film to an electron beam from the electron source that passes through the anode grid. We control the electron beam by controlling the bias voltage between the anode grid and the semiconductor structure. Another embodiment is a tool for curing a film.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: March 16, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Huang Liu, Bei Chao Zhang, Wuping Liu, John Leonard Sudijono, Liang Choo Hsia
  • Publication number: 20100044869
    Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.
    Type: Application
    Filed: August 22, 2008
    Publication date: February 25, 2010
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Bei Chao ZHANG, Chim Seng SEET, Juan Boon TAN, Fan ZHANG, Yong Chiang EE, Bo TAO, Tong Qing CHEN, Liang Choo HSIA
  • Publication number: 20100001370
    Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 7, 2010
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Haifeng Sheng, Fan Zhang, Juan Boon Tan, Bei Chao Zhang, Dong Kyun Sohn
  • Publication number: 20090315861
    Abstract: An interactive whiteboard system includes a combination electrical writable and dry erase marker, an interactive whiteboard to receive writing on the interactive whiteboard with the combination electrical writable and dry erase marker, and a computer operatively coupled to the interactive whiteboard to capture writing on the interactive whiteboard with the combination electrical writable and dry erase marker.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 24, 2009
    Applicant: INNOVATIVE MATERIAL SOLUTIONS, INC.
    Inventors: CHAO ZHANG, Bin HU, Shinhwa LI, Jen-Lung David TAI
  • Publication number: 20090294904
    Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first metallization layer over the substrate and electrically connected to the substrate; forming a viabar or a via group over the first metallization layer; and forming a second metallization layer over the first metallization layer and electrically connected to the first metallization layer through either the viabar or the via group.
    Type: Application
    Filed: June 3, 2008
    Publication date: December 3, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Shaoqing Zhang, Fan Zhang, Shao-fu Sanford Chu, Bei Chao Zhang
  • Patent number: 7622403
    Abstract: A semiconductor processing system with ultra low-K dielectric is provided including providing a substrate having an electronic circuit, forming an ultra low-K dielectric layer, having porogens, over the substrate, blocking an incoming radiation from a first region of the ultra low-K dielectric layer, evaporating the porogens from a second region of the ultra low-K dielectric layer by projecting the incoming radiation on the second region, and removing the ultra low-K dielectric layer in the first region with a developer.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: November 24, 2009
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yasri Yudhistira, Johnny Widodo, Bei Chao Zhang, Liang-Choo Hsia
  • Publication number: 20090286793
    Abstract: Compounds active on phosphodiesterase PDE4B are provided. Also provided herewith are compositions useful for treatment of PDE4B-mediated diseases or conditions, and methods for the use thereof.
    Type: Application
    Filed: July 20, 2009
    Publication date: November 19, 2009
    Inventors: Prabha N. Ibrahim, Hanna Cho, Bruce England, Sam Gillette, Dean R. Artis, Rebecca Zuckerman, Chao Zhang
  • Patent number: 7617365
    Abstract: Systems and methods can provide mirrored virtual targets and online synchronization and verification of the targets while avoiding deadlock, inconsistencies between members of the target, and false verification failures. A lock within the storage switch can limit the number of outstanding commands for a physical target to one during synchronization and verification operations. In one embodiment, a lock can be implemented as one or more resource tables maintaining an indication of the number of transfer ready signals available from physical targets. During typical write operations, deadlock can be avoided by determining whether each physical target for the mirrored operation can issue a transfer ready signal prior to issuing a command to the physical target. When a synchronization or verification operation begins, the maximum available number of transfer ready signals for each target can be decremented to one in order to limit the total number of outstanding commands for each target to one.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: November 10, 2009
    Assignee: EMC Corporation
    Inventors: Chao Zhang, Robert Tower Frey
  • Patent number: 7605168
    Abstract: Compounds are described that are active on PDE4. Also described are crystal structures of PDE4B determined using X-ray crystallography, the use of PDE4B crystals and structural information for identifying molecular scaffolds, for developing ligands that bind to and modulate PDE4B, and for identifying improved ligands based on known ligands.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: October 20, 2009
    Assignee: Plexxikon, Inc.
    Inventors: Prabha N. Ibrahim, Ryan Bremer, Sam Gillette, Hanna Cho, Marika Nespi, Shumeye Mamo, Chao Zhang, Dean R. Artis, Byunghun Lee, Rebecca Zuckerman
  • Publication number: 20090250818
    Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
    Type: Application
    Filed: June 17, 2009
    Publication date: October 8, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
  • Patent number: 7585859
    Abstract: Compounds active on phosphodiesterase PDE4B are provided. Also provided herewith are compositions useful for treatment of PDE4B-mediated diseases or conditions, and methods for the use thereof.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: September 8, 2009
    Assignee: Plexxikon, Inc.
    Inventors: Prabha N. Ibrahim, Hanna Cho, Bruce England, Sam Gillette, Dean R. Artis, Rebecca Zuckerman, Chao Zhang
  • Publication number: 20090221614
    Abstract: Inhibition of protein kinases having one or more cysteine residues within the ATP binding site is effected by contacting the kinase, per se or in a cell or subject, with an inhibitory-effective amount of a compound having a heterocyclic core structure comprised of two or more fused rings containing at least one nitrogen ring atom, and an electrophilic substituent that is capable of reacting with a cysteine residue within the ATP binding site of a kinase. Preferred compounds include certain pyrrolopyrimidines and oxindoles having such an electrophilic substituent and optionally an aromatic or heteroaromatic substituent that is capable of interacting with a threonine or smaller residue located in the gatekeeper position of the kinase. Kinases lacking such cysteine residues may be engineered or modified so that they are capable of being inhibited by such compounds by replacing a valine or other amino acid residue within the ATP binding site by a cysteine residue.
    Type: Application
    Filed: September 26, 2006
    Publication date: September 3, 2009
    Applicant: The Regents of the University of California
    Inventors: Jack Taunton, Michael Cohen, Kevin Shokat, Chao Zhang
  • Patent number: 7572806
    Abstract: Compounds are described that are active on PPARs, including pan-active compounds. Also described are methods for developing or identifying compounds having a desired selectivity profile.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: August 11, 2009
    Assignee: Plexxikon, Inc.
    Inventors: James Arnold, Dean R. Artis, Clarence R. Hurt, Prabha N. Ibrahim, Heike Krupka, Jack Lin, Michael V. Milburn, Weiru Wang, Chao Zhang
  • Publication number: 20090191792
    Abstract: The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 30, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Fan ZHANG, Lup San LEONG, Yong Kong SIEW, Bei Chao ZHANG
  • Publication number: 20090181988
    Abstract: This invention generally relates to pyrazolo pyrimidine derivatives useful as, inter alia, inhibitors of short chain dehydrogenase/reductase (SDR) family of NAD(P)(H) dependent oxido-reductases. More specifically, the invention relates to pyrazolo pyrimidine derivatives, including derivatives and analogs of SDR inhibitors, pharmaceutical compositions containing derivatives and analogs of SDR inhibitors, methods of making derivatives and analogs of SDR inhibitors and methods of use thereof.
    Type: Application
    Filed: August 19, 2008
    Publication date: July 16, 2009
    Applicant: The Regents of the University of California
    Inventors: Masahiro Tanaka, Chao Zhang, Kevan M. Shokat, Alma L. Burlingame, Kirk Hansen, Raynard L. Bateman, Stephen G. DiMagno
  • Publication number: 20090169102
    Abstract: A computer implemented method for fusing images taken by a plurality of cameras is disclosed, comprising the steps of: receiving a plurality of images of the same scene taken by the plurality of cameras; generating Laplacian pyramid images for each source image of the plurality of images; applying contrast normalization to the Laplacian pyramids images; performing pixel-level fusion on the Laplacian pyramid images based on a local salience measure that reduces aliasing artifacts to produce one salience-selected Laplacian pyramid image for each pyramid level; and combining the salience-selected Laplacian pyramid images into a fused image. Applying contrast normalization further comprises, for each Laplacian image at a given level: obtaining an energy image from the Laplacian image; determining a gain factor that is based on at least the energy image and a target contrast; and multiplying the Laplacian image by a gain factor to produce a normalized Laplacian image.
    Type: Application
    Filed: November 21, 2008
    Publication date: July 2, 2009
    Inventors: Chao Zhang, Peter Jeffrey Burt, Gooitzen Sieman van der Wal