Patents by Inventor Chen Zhang

Chen Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11154965
    Abstract: A hand tool includes a first jaw, a first handle fixed to the first jaw, a second jaw, and a second handle pivotally coupled to the second jaw, a link member, and an adjustment member. The adjustment member is operable to axially move a first end of the link member to vary a distance between the first and second jaws. The adjustment member includes an engagement surface engageable with the first end of the link member, a shank in threaded engagement with a bore in the first handle, and a flange extending from the shank opposite the engagement portion. The flange includes a first side, a second side opposite the first side, and an elongate opening extending through the first and second sides.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 26, 2021
    Assignee: Milwaukee Electric Tool Corporation
    Inventors: Steven W. Hyma, Chen Zhang Li
  • Publication number: 20210327769
    Abstract: A method of fabricating a complementary metal-oxide-semiconductor device is provided. The method includes forming a work function material layer segment on a gate dielectric layer over a first vertical fin and a bottom spacer layer on an n-type bottom source/drain adjoining the first vertical fin on a first region of a substrate, wherein the gate dielectric layer is also over a second vertical fin, bottom spacer layer on a p-type bottom source/drain adjoining the second vertical fin on a second region. The method further includes heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value, forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin, and growing a top source/drain on each of the vertical fins.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 21, 2021
    Inventors: Tenko Yamashita, Chen Zhang, Teresa Jacqueline Wu
  • Patent number: 11148488
    Abstract: A vehicle system is configured to control a trailer alignment routine. The system comprises a hitch ball mounted on a vehicle and a controller configured to identify a coupler position of a trailer. The controller is further configured to control motion of the vehicle to an aligned position, wherein the hitch ball is aligned with the coupler position. In response to the aligned position, the controller activates a service brake holding the vehicle and while maintaining the service brake activation, the controller activates a parking brake.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: October 19, 2021
    Assignee: Ford Global Technologies, LLC
    Inventors: Luke Niewiadomski, Shannon Brooks-Lehnert, Roger Arnold Trombley, Kenneth Michael Mayer, Chen Zhang
  • Patent number: 11152507
    Abstract: Techniques regarding one or more VFETs operably coupled to bottom contacts with low electrical resistance are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a vertical field-effect transistor device that can comprise a semiconductor fin positioned on a source/drain region, which can comprise a semiconductor substrate. The apparatus can also comprise a metal contact layer positioned on the source/drain region and at least partially surrounding a base of the semiconductor fin. Further, the metal contact layer can be in electrical communication with the source/drain region.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chen Zhang, Tenko Yamashita, Terence B Hook, Brent Alan Anderson
  • Publication number: 20210320035
    Abstract: Semiconductor devices, and methods of forming the same, include forming a stack of channel layers, including an upper device region and a lower device region. The upper device region is separated from the lower device region by a dielectric spacer layer. A first work function metal layer is formed on the channel layers in the lower device region. A height of the first work function metal layer does not rise above the dielectric spacer layer. A second work function metal layer is formed on the channel layers in the upper device region.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 14, 2021
    Inventors: Ruilong Xie, Chen Zhang, Kangguo Cheng, Juntao Li
  • Patent number: 11144057
    Abstract: Provided is an autonomous versatile robotic chassis, including: a chassis; a set of wheels coupled to the chassis; one or more motors to drive the set of wheels; one or more mounting elements; at least one food equipment coupled to the robotic chassis using the one or more mounting elements; a processor; one or more sensors; a camera; and a tangible, non-transitory, machine readable medium storing instructions that when executed by the processor effectuates operations including: generating, with the processor, a map of an environment; localizing, with the processor, the robotic chassis; receiving, with the processor, a request for delivery of a food item to a first location; generating, with the processor, a movement path to the first location from a current location; and instructing, with the processor, the robotic chassis to transport the food item to the first location by navigating along the movement path.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 12, 2021
    Assignee: AI Incorporated
    Inventors: Ali Ebrahimi Afrouzi, Lukas Fath, Shahin Fathi Djalali, Chen Zhang
  • Patent number: 11144285
    Abstract: A server and method for converting a textual data prompt embedded within a graphical user interface (GUI) to a widget. Parameters of a textual data prompt, which was previously received from a first computing device, are compared to additional parameters associated with widget. A first match and a second match between the parameters and the additional parameters associated with a first widget and a second widget, respectively, of the widgets is identified. In response to determining that a percentage of the first match exceeds a confidence threshold and a percentage of the second match fails to exceed the confidence threshold, the first widget embedded within the GUI on a second computing device is generated. A first response to the textual data prompt by a user associated with the second computing device is received. The first response is displayed as textual data embedded within the GUI of the first computing device.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chih-Hsiung Liu, Chen Zhang, Jian Gang JG Jin, Wei EY Li, Li Qiang MX Xue
  • Patent number: 11137861
    Abstract: An electronic device such as a speaker device may have a curved housing characterized by a vertical longitudinal axis. A layer of fabric may cover the curved housing. A touch sensor may be used to detect touch input on the layer of fabric. The touch sensor may include capacitive touch sensor electrodes including drive lines and sense lines. In some arrangements, the touch sensor is formed from conductive strands in the layer of fabric. In other arrangements, the touch sensor is formed from conductive traces on a substrate. The substrate may be formed from portions of the curved housing or may be formed from a layer that is separate from the housing. Light-emitting components and/or fabric with different visual characteristics may be used to mark where the touch-sensitive regions of the fabric are located. The touch-sensitive regions may be shaped as media control symbols.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: October 5, 2021
    Assignee: Apple Inc.
    Inventors: Zhengyu Li, Elvis M. Kibiti, Ming Gao, Qiliang Xu, Chen Zhang
  • Patent number: 11139215
    Abstract: A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: October 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Tenko Yamashita, Takashi Ando, Oleg Gluschenkov, Chen Zhang, Koji Watanabe
  • Publication number: 20210305364
    Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Juntao Li, Kangguo Cheng, Chen Zhang, Zhenxing Bi
  • Publication number: 20210296494
    Abstract: A vertical transport field-effect transistor array includes continuous spacers at cell edges that are formed following a replacement metal gate process. Techniques for fabricating the transistor array include forming trenches extending along the fin edges of the array to provide access to sacrificial gates, replacing the sacrificial gates with gate stacks, and forming the continuous spacers to encapsulate the gate stacks once formed. Removal of interlevel dielectric material from the array is not required for gate replacement. Bottom source/drain contacts may be formed in the trenches and in adjoining relation to the continuous spacers.
    Type: Application
    Filed: March 17, 2020
    Publication date: September 23, 2021
    Inventors: Ruilong Xie, Chen Zhang, Kangguo Cheng, Julien Frougier
  • Publication number: 20210296396
    Abstract: A semiconductor structure that includes a metal layer in a first interlayer dielectric that is above a semiconductor device. The semiconductor structure includes an embedded memory device on the metal layer. The embedded memory device has a first metal contact surrounded by a second interlayer dielectric. Additionally, the semiconductor structure includes a thin film transistor on the first metal contact. The thin film transistor is surrounded by a third interlayer dielectric. The third interlayer dielectric is over a portion of the embedded memory device and a portion of the second interlayer dielectric. The semiconductor structure includes a first portion of a channel of the thin film transistor covered a gate structure, where the channel is a layer of indium tin oxide.
    Type: Application
    Filed: March 18, 2020
    Publication date: September 23, 2021
    Inventors: Heng Wu, Julien Frougier, Bruce B. Doris, Chen Zhang, Ruilong Xie
  • Patent number: 11124234
    Abstract: A driver assistance system for a vehicle having a hitch includes a trailer detection system, a steering system, and a controller. The controller determines that a trailer is not coupled with the hitch and outputs a reverse hitching path control signal to the steering system and determines that the trailer is coupled with the hitch and outputs a trailer backing path control signal to the steering system.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 21, 2021
    Assignee: Ford Global Technologies, LLC
    Inventors: Luke Niewiadomski, Donald Jacob Mattern, Roger Arnold Trombley, Aleksey Shepelev, Chen Zhang
  • Patent number: 11119911
    Abstract: Heterogeneous garbage types are collected by scanning all of the service items to identify all of the service types that are included within the service items, identifying garbage collection components that correspond with the service types, and then collecting garbage for the corresponding target service types by using the corresponding garbage collection components.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: September 14, 2021
    Assignee: Alibaba Group Holding Limited
    Inventors: Jie Zhang, Chen Zhang, Le He, Yingjie Shi, Yan Huang
  • Patent number: 11121215
    Abstract: A technique relates to a semiconductor device. A stack includes two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack. A separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires. A source or a drain formed on sides of the stack.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Chen Zhang, Xin Miao
  • Publication number: 20210280578
    Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 9, 2021
    Inventors: Heng WU, Chen ZHANG, Kangguo CHENG, Tenko YAMASHITA, Joshua M. RUBIN
  • Patent number: 11115374
    Abstract: A method is provided in one example embodiment and includes detecting by a first network element at a first data center site a local connection of an endpoint identifier (“EID”), in which the EID was previously locally connected to a second network element at a second data center site and notifying a mapping server of the local connection of the EID to the first network element. The method further includes receiving from the mapping server identifying information for the second network element and communicating with the second network element using the identifying information to obtain service information for traffic associated with the EID. The method may also include applying a service identified by the service information to outgoing traffic from the EID as well as applying a service identified by the service information to incoming traffic for the EID.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: September 7, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Zhang Xiaopu, Li Yan, Marco Pessi, Wei Ling, Michael David Tracy, Chen Zhang, Darrel Jay Lewis
  • Publication number: 20210273077
    Abstract: A semiconductor structure, and a method for forming the same includes an amorphous semiconductor layer in contact with a top surface of a channel fin extending vertically from a bottom source/drain located above a substrate. A hard mask memorization layer is formed directly above the amorphous semiconductor layer, portions of the amorphous semiconductor layer in contact with the top surface of the channel fin are recrystallized forming recrystallized regions. The amorphous semiconductor layer is selective removed and a second dielectric layer is deposited to form a top spacer. The hard mask memorization layer and the recrystallized regions are removed, and a first epitaxial region is formed above the channel fin followed by a second epitaxial region positioned above the first epitaxial region and between the second dielectric layer forming a top source/drain of the semiconductor structure.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 2, 2021
    Inventors: Ruilong Xie, Chun-Chen Yeh, Alexander Reznicek, Chen Zhang
  • Patent number: 11107905
    Abstract: A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Publication number: 20210265422
    Abstract: A semiconductor device including an MRAM (magnetoresistive random-access memory) cell disposed above and in electrical contact with a VFET (vertical field effect transistor) access transistor.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 26, 2021
    Inventors: Heng Wu, Alexander Reznicek, Ruilong Xie, Julien Frougier, Chen Zhang, Bruce B. Doris