Abstract: A method for improving a process model by measuring a feature on a printed design that was constructed based in part on a target design is disclosed. The method includes obtaining a) an image of the printed design from an image capture device and b) contours based on shapes in the image. The method also includes identifying, by a pattern recognition program, patterns on the target design that include the feature and determining coordinates, on the contours, that correspond to the feature. The method further includes improving the process model by at least a) providing a measurement of the feature based on the coordinates and b) calibrating the process model based on a comparison of the measurement with a corresponding feature in the target design.

Abstract: A method for manufacturing a semiconductor device includes forming a first plurality of fins in a first device region on a substrate, forming a second plurality of fins in a second device region on the substrate, forming bottom source/drain regions on the substrate and around lower portions of each of the first and second plurality of fins in the first and second device regions, forming a dummy spacer layer on the bottom source/drain region in the first device region, wherein the dummy spacer layer includes one or more dopants, and forming a plurality of doped regions in the first and second plurality of fins in the first and second device regions, wherein the plurality of doped regions in the first device region extend to a greater height on the first plurality of fins than the plurality of doped regions in the second device region on the second plurality of fins.

Abstract: A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a first electrode upon a conductive contact of an underlying semiconductor device, forming a first vertical magnetoresistive random-access memory (MRAM) cell stack upon the first electrode, forming a spin-Hall-effect (SHE) layer above and in electrical contact with the MRAM cell stack, forming a protective dielectric layer covering a portion of the SHE layer, forming a second vertical MRAM cell stack above and in electrical contact with an exposed portion of the SHE layer, forming a second electrode above and in electrical contact with the second vertical MRAM cell stack, and forming a metal contact above and in electrical connection with the second electrode.

Abstract: An embodiment of the invention may include a method of forming a semiconductor structure, and the resulting semiconductor structure. The method may include removing a gate region from a layered stack located on a source/drain layer. The layered stack includes a first spacer located on the source drain layer, a dummy layer located on the first spacer, and a second spacer located on the dummy layer. The method may include forming a channel material above the source/drain layer in the gate region. The method may include forming a top source/drain on the channel material. The method may include forming a hardmask surrounding the top source/drain. The method may include removing a portion of the layered stack that is not beneath the hardmask.

Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.

Abstract: A vehicle system comprises a hitch ball mounted on a vehicle and a controller configured to identify a coupler position of a trailer. The controller is further configured to control motion of the vehicle aligning the hitch ball with the coupler position and monitor a height of the coupler relative to the hitch ball. In response to the coupler height being less than a height of the hitch ball, the controller is configured to stop the motion of the vehicle.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.

Abstract: A method of fabricating adjacent vertical fins with top source/drains having an air spacer and a self-aligned top junction, including, forming two or more vertical fins on a bottom source/drain, forming a top source/drain on each of the two or more vertical fins, wherein the top source/drains are formed to a size that leaves a gap between the adjacent vertical fins, and forming a source/drain liner on the top source/drains, where the source/drain liner occludes the gap between adjacent top source/drains to form a void space between adjacent vertical fins.

Abstract: The subject matter of this specification can be embodied in, among other things, a method for operating a hydraulic free piston engine includes receiving, at an engine controller for a hydraulic free piston engine, an energy parameter that is representative of an amount of fluid energy to be output by the engine, and a measured fluid pressure value of a fluid load of the engine, determining a piston trajectory of a piston within a hydraulic chamber of the engine, determining a fuel volume value and a servo valve actuation parameter, based on the energy parameter and the measured fluid pressure value, providing a fuel control signal to a fuel control device of the engine based on the fuel volume value, and providing, based on the servo valve actuation parameter and the piston trajectory, a servo valve control signal to a servo valve.

Abstract: A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.

Abstract: A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

Abstract: Embodiments of the invention are directed to a first nanosheet transistor device and a second nanosheet transistor device formed on a substrate. The first nanosheet transistor includes a first inner spacer having a first inner spacer thickness, along with a first gate dielectric having a first gate dielectric thickness. The second nanosheet transistor includes a second inner spacer having a second inner spacer thickness, along with a second gate dielectric having a second gate dielectric thickness. The first inner spacer thickness is greater than the second inner spacer thickness. The first gate dielectric thickness is greater than the second gate dielectric thickness. The first inner spacer thickness combined with the first gate dielectric thickness defines a first combined thickness. The second inner spacer thickness combined with the second gate dielectric thickness defines a second combined thickness. The first combined thickness is substantially equal to the second combined thickness.

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

Abstract: Disclosed in the present invention are a compound represented by formula (I), a tautomer thereof or a pharmaceutically acceptable salt, and applications thereof in the preparation of drugs for treating HBV-related diseases.

Abstract: Three-dimensional, living, self-regenerative structures of predetermined geometry comprising solidified print material comprising a biofilm of Bacillus subtilis comprise a TasA-R protein, wherein R is a recombinant, heterologous functional group, wherein the TasA-R provides a preferably tunable physiochemical property like viscosity, reactivity, affinity as a function of the R group.

Abstract: Methods are provided to construct field-effect transistors comprising low-resistance metallic gate structures. A field-effect transistor includes a nanosheet stack and a metal gate which covers a gate region of the nanosheet stack. The nanosheet stack includes nanosheet channel layers and an etch stop layer disposed above an upper nanosheet channel layer. The metal gate includes a work function metal which encapsulates the nanosheet channel layers, and a gate electrode disposed above and in contact with the work function metal. An upper surface of the work function metal is recessed to be substantially coplanar with the etch stop layer. The gate electrode has a resistivity which is less than a resistivity of the work function metal. The etch stop layer protects the portion of the work function metal disposed between the etch stop layer and the upper nanosheet channel layer from being etched when recessing the work function metal.

Abstract: Methods, apparatuses, mobile terminals, and cameras for recognizing a photographed object are provided. The recognition method includes starting a photographing device of a terminal to auto-focus a photographed object in response to receiving a photographing instruction; obtaining a post-focusing focal distance of the photographing device after the photographing device successfully focuses on the photographed object; and determining whether an object type of the photographed object is a photograph based on the post-focusing focal distance. The present application resolves the technical problem of the high complexity associated with the schemes for recognizing a remade photograph in existing technologies.

Abstract: The present invention relates to a method for preparing physically modified starch by utilizing heating and freezing-thawing (FT) on starch or a starch-gum mixture obtained by adding gum to starch. According to the method for preparing physically modified starch of the present invention, the weakness of natural starch can be supplemented, and heat and shear stability, gel-forming ability, and storage stability thereof can be improved. Especially, modified starch with a significantly improved modification effect can be produced by the addition of gum and the heating and freezing-thawing treatment. The present invention can significantly improve quality and storage stability of various starchy foods through a simple modification procedure, and thus it is expected that the present invention can be variously utilized in industry field of food including starchy food.

Abstract: Forming a fin, where the fin includes a nanowire stack on a semiconductor substrate, where the nanowire stack includes a plurality of silicon layers and a plurality of silicon germanium layers stacked one on top of the other in an alternating fashion, removing a portion of the fin to form an opening and expose vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layer, and epitaxially growing a source drain region/structure in the opening from the exposed vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers, where the source drain region/structure substantially fills the opening.