Abstract: Methods are provided to construct field-effect transistors comprising low-resistance metallic gate structures. A field-effect transistor includes a nanosheet stack and a metal gate which covers a gate region of the nanosheet stack. The nanosheet stack includes nanosheet channel layers and an etch stop layer disposed above an upper nanosheet channel layer. The metal gate includes a work function metal which encapsulates the nanosheet channel layers, and a gate electrode disposed above and in contact with the work function metal. An upper surface of the work function metal is recessed to be substantially coplanar with the etch stop layer. The gate electrode has a resistivity which is less than a resistivity of the work function metal. The etch stop layer protects the portion of the work function metal disposed between the etch stop layer and the upper nanosheet channel layer from being etched when recessing the work function metal.

Abstract: Included is a method of path planning for a robotic device, including: receiving, by a processor of the robotic device, a sequence of one or more commands; executing, via the robotic device, the sequence of one or more commands; saving the sequence of one or more commands in memory of the robotic device after a predetermined amount of time from receiving a most recent one or more commands; and re-executing the saved sequence of one or more commands.

Abstract: A tactile sensation providing method and device. The tactile sensation providing method includes: generating a first tactile sensation based on information of a contour attribute of a visual object; generating a second tactile sensation based on information of a texture attribute of the visual object; and generating a third tactile sensation based on information of a roughness attribute of the visual object.

Abstract: Metal-assisted chemical etching is employed to form a three-dimensional (3D) resistive random access memory (ReRAM) in which the etching aspect ratio limit is extended and the top trench and bottom trench CD uniformity is improved. The 3D ReRAM includes a metal catalyst located between a bitline electrode and a selector device. Further, the 3D ReRAM includes vertically stacked and spaced apart replacement wordline electrodes that are located adjacent to the bitline electrode.

Abstract: Provided is an autonomous hospital bed including: a frame; wheels; motors to drive the wheels; a controller in communication with the motors; sensors; a processor; a tangible, non-transitory, machine readable medium storing instructions that when executed by the processor effectuate operations including: capturing, with the sensors, depth data indicating distances to objects within an environment of the hospital bed and directions of the distances; capturing, with the sensors, movement data indicating movement distance and direction of the hospital bed; generating, with the processor, a map of the environment using the depth and movement data; generating, with the processor, a movement path to a first location; instructing, with the processor, motor drivers of the wheels to move the hospital bed along the movement path; and, inferring, with the processor, a location of the hospital bed within the environment as the hospital bed navigates along the movement path.

Abstract: The invention provides a peptide amide compound represented by the general general formula (I), a preparation method thereof, and a medical application thereof. The compound has a novel structure, better biological activity, and better analgesic effect.

Abstract: A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.

Abstract: In embodiments of the present disclosure, there is provided an approach for neural network model compression based on bank-balanced sparsity. In embodiments of the present disclosure, a set of weight parameters, such as a weight matrix, in a neural network is divided into a plurality of equal-sized banks in terms of number of elements, and then all of the equal-sized banks are pruned at the same sparsity level. In this way, each pruned bank will have the same number of non-zero elements, which is suitable for hardware speedup. Moreover, since each bank is pruned independently in a fine granularity, the model accuracy can be ensured. Thus, according to embodiments of the present disclosure, the neural network compression method based on bank-balanced sparsity can achieve both high model accuracy and high hardware speedup.

Abstract: An integrated circuit having logic and static random-access memory (SRAM) devices includes at least three active regions with gate terminals. Dielectric pillars are disposed between the active regions of the integrated circuit. A pillar is disposed symmetrically between two active regions of the logic device. A pillar is disposed asymmetrically between a p-channel field effect transistor (pFET), and an n-channel field effect transistor (nFET) of the SRAM device.

Abstract: A semiconductor wafer includes a substrate. The substrate includes a first substrate region doped with a first dopant and a second substrate region doped with a second dopant. The semiconductor wafer further includes a buried oxide (BOX) layer formed on the substrate and a channel layer formed above the BOX layer. A first transistor is operably disposed on the substrate in the first substrate region and a second transistor is operably disposed on the substrate in the second substrate region. First doped source and drain structures electrically connected to the substrate in the first substrate region and separated by portions of the channel layer and the BOX layer. Second doped source and drain structures electrically connected to the substrate in the second substrate region and separated by portions of the channel layer and the BOX layer.

Abstract: A semiconductor device includes a semiconductor wafer having one or more suspended nanosheet extending between first and second source/drain regions. A gate structure wraps around the nanosheet stack to define a channel region located between the source/drain regions. The semiconductor device further includes a first all-around source/drain contact formed in the first source/drain region and a second all-around source/drain contact formed in the second source/drain region. The first and second all-around source/drain contacts each include a source/drain epitaxy structure and an electrically conductive external portion that encapsulates the source/drain epitaxy structure.

Abstract: A semiconductor device includes a stacked transistor memory cell. The stacked transistor memory cell includes a bottom tier including a plurality of bottom transistors including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal being electrically disconnected from other transistors of the stacked transistor memory cell. The stacked transistor memory cell further includes a top tier including a at least one top transistor, and a cross-coupling including epitaxial region (epi) connections and gate to epi connections between the top tier and the bottom tier.

Abstract: A semiconductor device includes a stacked transistor memory cell. The stacked transistor memory cell includes a bottom tier including a plurality of bottom transistors including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal being electrically disconnected from other transistors of the stacked transistor memory cell. The stacked transistor memory cell further includes a top tier including a at least one top transistor, and a cross-coupling including epitaxial region (epi) connections and gate to epi connections between the top tier and the bottom tier.

Abstract: A method for detecting a slow node includes: obtaining a generated record for a first storage node, the generated record including a storage node generation time, and a number of times and consuming time for transmitting data to second storage nodes other than the first storage node; obtaining a valid record from the generated record, the valid record being generated within a preset time period, and the preset time period being within a time period between the storage node generation time and a current time; determining an average consuming time for the first storage node transmitting the data to each of the second storage nodes, based on the number of times and the consuming time in the valid record; and detecting the slow node in the second storage nodes based on the average consuming time.

Abstract: A method is presented for constructing mechanically stable fins. The method includes forming a fin stack including a plurality of sacrificial layers, recessing the fin stack to form channel fins, depositing a first type epitaxy between the channel fins, depositing a dielectric region over the first type epitaxy, depositing a second type epitaxy over the dielectric region, and removing the plurality of sacrificial layers resulting in formation of a plurality of gaps. The method further includes filling a first set of the plurality of gaps with a p-type work function metal (WFM) to form a p-type field effect transistor (pFET) structure and filling a second set of the plurality of gaps with an n-type WFM to form an n-type field effect transistor (nFET) structure, where the nFET structure is stacked over the pFET structure.

Abstract: A method for identifying a trailer connection for a vehicle includes storing a plurality of connection configurations as saved configurations. The connection configurations identify a hitch compatibility of a coupler of a trailer to a hitch assembly. The method further comprises capturing image data depicting the hitch assembly and processing the image data. Based on the processing of the image data, the method further identifies a detected hitch configuration of the hitch assembly as a first hitch configuration of the saved configurations.

Abstract: A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.

Abstract: A method for fabricating a semiconductor device to account for misalignment includes forming a top via on a first conductive line formed on a substrate, forming liners each using a first dielectric material, including forming first and second liners to a first height along sidewalls of the top via, forming dielectric layers, including forming first and second dielectric layers on the first conductive line to the first height and adjacent to the first and second liners, respectively, recessing the top via to a second height, and forming an additional dielectric layer on the recessed top via to the first height using a second dielectric material. The first and second dielectric materials are selected to compensate for potential misalignment between the first conductive line and the top via.

Abstract: Embodiments of the invention are directed to a method of forming a nanosheet transistor. A non-limiting example of the method includes forming a nanosheet stack having alternating layers of channel nanosheets and sacrificial nanosheets, wherein each of the layers of channel nanosheets includes a first type of semiconductor material, and wherein each of the layers of sacrificial nanosheets includes a second type of semiconductor material. The layers of sacrificial nanosheets are removed from the nanosheet stack, and layers of replacement sacrificial nanosheets are formed in the spaces that were occupied by the sacrificial nanosheets. Each of the layers of replacement sacrificial nanosheets includes a first type of non-semiconductor material.