Patents by Inventor Cheng Han

Cheng Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240377886
    Abstract: A system and a method for interacting with an extended reality environment are provided. The method includes: generating, by a touch sensor with a detection area, a touch signal, wherein the touch sensor is included in a ring-type controller; providing, by a head-mounted display, an extended reality scene; determining, by the head-mounted display, whether an object is in the detection area according to the touch signal; in response to determining the object is in the detection area, generating, by the head-mounted display, a first command according to a movement of the ring-type controller; and moving, by the head-mounted display, a cursor in the extended reality scene according to the first command.
    Type: Application
    Filed: March 13, 2024
    Publication date: November 14, 2024
    Applicant: HTC Corporation
    Inventors: Tzu-Yin Chang, Cheng-Han Hsieh, Chih Chien Chen, Su Kang Chou
  • Publication number: 20240377766
    Abstract: An extreme ultraviolet (EUV) photolithography system cleans debris from an EUV reticle. The system includes a cleaning electrode configured to be positioned adjacent the EUV reticle. The system includes a voltage source that helps draw debris from the EUV reticle toward the cleaning electrode by applying a voltage of alternating polarity to the cleaning electrode.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Yen-Hui LI, Cheng-Han YEH, Tzung-Chi FU
  • Patent number: 12142683
    Abstract: A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee, Pei-Shan Lee
  • Patent number: 12142681
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20240369911
    Abstract: A camera module includes a frame, a camera body, an appearance component, and a transparent cover. The frame includes a first opening. The camera body is disposed in the frame and includes a lens. The first opening corresponds to and exposes the lens. The appearance component is disposed on the frame and includes a second opening corresponding to and exposing the lens and a framing portion protruding from a top surface of the appearance component and framing the second opening. The transparent cover is engaged with the framing portion and covers the lens.
    Type: Application
    Filed: October 12, 2023
    Publication date: November 7, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Cheng-Han Chung, Chen-Chuan Shieh
  • Publication number: 20240372001
    Abstract: A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Shahaji B. More, Cheng-Han Lee, Shih-Chieh Chang
  • Publication number: 20240371941
    Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. MORE, Huai-Tei Yang, Zheng-Yang Pan, Shin-Cieh Chang, Chun-Chieh Wang, Cheng-Han Lee
  • Publication number: 20240371982
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. MORE, Chien LIN, Cheng-Han LEE, Shih-Chieh CHANG, Shu KUAN
  • Patent number: 12135489
    Abstract: An anti-peeping panel, a preparation method, a driving method, and a display device. The anti-peeping panel includes: a first substrate; a second substrate; a composite material layer; first and second transparent electrode layers.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: November 5, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Cheng Han, Xin Li, Xing Fan, Qixiao Wu, Songquan Wu
  • Patent number: 12129273
    Abstract: Compounds for use in prevention and/or treatment of pain are disclosed. The compounds are derived by conjugation of N6-(4-hydroxybenzyl)adenosine and analogous compounds with amino acids or peptides. In one embodiment of the invention, the compound is 5?-glycylcarbonyl-N6-(4-hydroxybenzyl)adenosine (I-a1). In another embodiment of the invention, the compound is 5?-deoxy-5?-(N?-glycylureido)-N6-(4-hydroxybenzyl)adenosine (I-d1). Also disclosed are methods of making and using the same.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: October 29, 2024
    Assignee: ACADEMIA SINICA
    Inventors: Chih-Cheng Chen, Jim-Min Fang, Cheng-Han Lee, Jen-Yao Chang
  • Publication number: 20240353755
    Abstract: A method includes forming a metallic resist layer over a substrate and patterning the metallic resist layer to form a metallic resist pattern over the substrate. An etch resistant layer composition including an inorganic component, an organic component, or a combination thereof is formed over the metallic resist pattern to form an etch resistant layer.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 24, 2024
    Inventors: Shi-Cheng WANG, Cheng-Han Wu, Ching-Yu Chang, Ya-Ching Chang
  • Publication number: 20240353956
    Abstract: The present invention relates to a touch module and a touch screen. The touch module includes a touch panel located on the display module, a main circuit board located outside the casing of the touch screen, a plurality of signal cables connecting the touch panel and the main circuit board, and an equal potential wiring. By setting an equal potential wiring in the touch module to electrically bridge any two signal cables, a short circuit is formed between the shielding layers of the signal cables so that the potentials of different signal cables can be equalized to make the signal cables roughly the same degree of electrostatic or electromagnetic interference from the environment. By making the signals obtained by the signal cables be disturbed to approximately the same degree, the touch module can accurately determine the touch position.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 24, 2024
    Inventors: Chin-Fu CHANG, Shang-Tai YEH, Cheng-Han LEE
  • Patent number: 12125915
    Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes forming, over a substrate, a fin-shaped structure that includes a plurality of channel layers interleaved by a plurality of sacrificial layers, recessing a source/drain region of the fin-shaped structure to form a source/drain recess that extends into the substrate and exposes a portion of the substrate, selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses, forming inner spacers in the inner spacer recesses, selectively forming a buffer semiconductor layer on the exposed portion of the substrate, selectively depositing a first epitaxial layer on sidewalls of the plurality of channel layer and the buffer semiconductor layer such that a top surface of the buffer semiconductor layer is completely covered by the first epitaxial layer, and depositing a second epitaxial layer over the first epitaxial layer and the inner spacers.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. More, Cheng-Han Lee
  • Publication number: 20240347288
    Abstract: A key structure including a base plate, a thin film circuit, a display key, an elastic supporting member, and a lifting mechanism is provided. The thin film circuit is disposed on the base plate. The display key is disposed above the thin film circuit. The elastic supporting member is disposed between the display key and the thin film circuit. The lifting mechanism is disposed between the display key and the base plate.
    Type: Application
    Filed: November 21, 2023
    Publication date: October 17, 2024
    Applicant: Acer Incorporated
    Inventors: Hung-Chi Chen, Cheng-Han Lin, Chuan-Hua Wang, Po-Yi Lee, Pin-Chueh Lin
  • Publication number: 20240346476
    Abstract: Systems and methods for processing transactions using a digital payment platform.
    Type: Application
    Filed: April 22, 2024
    Publication date: October 17, 2024
    Inventors: Osama Bedier, Ray Tanaka, Victor Chau, Charles Feng, Cheng Han Lee, Lubab Al-Khawaja
  • Publication number: 20240345130
    Abstract: A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Ting Chen, Cheng-Han Huang, Kuang-Hua Wang
  • Patent number: 12119394
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. More, Chien Lin, Cheng-Han Lee, Shih-Chieh Chang, Shu Kuan
  • Patent number: D1046849
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: October 15, 2024
    Assignee: Acer Incorporated
    Inventors: Hsueh-Wei Chung, Pao-Ching Huang, Cheng-Han Lin
  • Patent number: D1046851
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: October 15, 2024
    Assignee: Acer Incorporated
    Inventors: Cheng-Han Lin, Pao-Ching Huang, Hsueh-Wei Chung
  • Patent number: D1049412
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: October 29, 2024
    Assignee: CYTENA BIOPROCESS SOLUTIONS CO., LTD.
    Inventors: Cheng-Han Tsai, Erik Gatenholm, Markus Grip, Isak Folenius, Héctor Martínez, Yeu-Fan Shih, Li-Wei Yeh