Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, and a dielectric isolation plug. The semiconductor fin extends along a first direction above a substrate and includes a silicon germanium layer and a silicon layer over the silicon germanium layer. The gate structure extends across the semiconductor fin along a second direction perpendicular to the first direction. The dielectric isolation plug extends downwardly from a top surface of the silicon layer into the silicon germanium layer when viewed in a cross section taken along the first direction.

Abstract: The present disclosure provides a dog nose print recognition method and system. The dog nose print recognition method includes: collecting a nose image of a dog, acquiring the nose image, and processing the nose image to obtain a plurality of regional images to be recognized; performing key point detection on the plurality of regional images to be recognized to obtain key points corresponding to the regional images to be recognized, and using the key points to perform alignment processing of the regional images to be recognized to obtain aligned regional images to be recognized; and performing dog nose print feature vector extraction and recognition on the aligned regional images to be recognized, and determining a dog identity recognition result through the dog nose print feature vector extraction and recognition. The system includes modules corresponding to the steps of the method.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array.

Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

Abstract: An intelligent energy storage system, electrically connected to an external power source and a load, including a first energy storage device, a second energy storage device, at least one converter and a controller. The first energy storage device is adapted for storing electrical energy. The second energy storage device is electrically connected to the external power source and the load. The converter is electrically connected between the first and the second energy storage device. The controller is configured to detect at least one electrical property of the first or the second energy storage device to regulate an output voltage and current of the converter. In an energy storage mode, the external power source is used to charge the first energy storage device through the second energy storage device. In an energy transfer mode, the first energy storage device is used as power source to charge the second energy storage device.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: The present disclosure provides a method and system for optimizing first-diffraction-order reconstruction of holograms, a device and a medium, and relates to the field of image processing. The method includes: acquiring a target image; determining a target image light field according to the target image; calculating a target diffraction field for the target image light field by performing backward propagation by a set distance; constructing a U-Net network model; and inputting the target diffraction field into a trained U-Net network model to acquire an optimized hologram. The trained U-Net network model is obtained by constructing a U-Net network model and training and optimizing the U-Net network model, thereby continuously improving the quality of the zero-diffraction-order reconstructed image of the initial hologram and finally achieving the effect of optimizing the first-diffraction-order reconstructed image of the hologram.

Abstract: A module device on a first substrate includes a power module, a housing, a pair of locking structures. The housing covers the power module. The locking structures are installed on a pair of opposite sides of the housing, and the locking structure includes a main body, a locking ring, a pair of ribs and anchoring portions. The locking ring extends from a side toward an inner side of the main body, and is a double-ring structure, which includes an inner and an outer ring. A first side of the outer ring is connected to the main body, a second side of the outer ring is connected to the inner ring. The ribs extend along a normal direction of the top surface of the main body. The anchoring portions are disposed at the end of the ribs, and an extending direction is perpendicular to an extending direction of the rib.

Abstract: A radiation therapy system may include a magnetic resonance imaging (MRI) device configured to acquire MRI data with respect to a region of interest (ROI). The MRI device may include a main magnet that is around a longitudinal axis and configured to generate a magnetic field. The MRI device may also include a radiation therapy device configured to perform a treatment on at least one portion of the ROI by delivering, based on the MRI data, therapeutic radiation to the at least one portion of the ROI. The radiation therapy device may be rotatable around the longitudinal axis. The MRI device may also include a first shielding structure configured to provide interference shielding for the MRI device or the radiation therapy device. The radiation therapy device may be rotatable relative to the first shielding structure around the longitudinal axis.

Abstract: Embodiments of the disclosure provide a method and apparatus for running a service, and an electronic device. An embodiment of the method includes: determining a target deployment manner of a graphics processing unit (GPU) according to performance data of each service in a service set, where the deployment manner includes: dividing the GPU into sub-GPUs of a respective size and determining a service configured to be run by each sub-GPU; and switching, for the service in the service set, running of the service from a sub-GPU indicated by a current deployment manner to a sub-GPU indicated by the target deployment manner. According to the embodiment, waste of the GPU can be reduced by running a plurality of services on the GPU.

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Abstract: An aqueous dispersion of polymeric particles comprising an emulsion polymer and a polyalkylene oxide with a weight average molecular weight in the range of 450 to 1,500 g/mole, and an aqueous coating composition with low VOCs comprising the aqueous dispersion and providing coatings made therefrom with improved water whitening resistance and hardness.

Abstract: A light-emitting diode device includes an epitaxial structure that contains first-type and second-type semiconductor units and an active layer interposed therebetween, a light transmittable dielectric element that is disposed on the first-type semiconductor unit opposite to the active layer and is formed with a first through hole, an adhesive layer that is disposed on the dielectric element and is formed with a second through hole corresponding in position to the first through hole, and a metal contact element that is disposed on the adhesive layer. The adhesive layer has a thickness of at most one fifth of that of the dielectric element. The metal contact element extends into the first and second through holes, and electrically contacts the first-type semiconductor unit. A method for manufacturing the LED device is also disclosed.

Abstract: A photographing device for a vehicle and relates to the field of automatic driving technology is disclosed. The specific solution is that the photographing device includes a seat; a camera mounted on the seat; a lens holder mounted on the seat and rotatable relative to the seat; a transparent lens mounted on the lens holder and arranged opposite to the camera; and a driving assembly connected with the lens holder to drive the lens holder to rotate relative to the base.

Abstract: A method includes forming a semiconductor fin on a substrate; conformally forming a dielectric layer over the semiconductor fin; depositing an oxide layer over the dielectric layer; etching back the oxide layer to lower a top surface of the oxide layer to a level below a top surface of the semiconductor fin; conformally forming a metal oxide layer over the semiconductor fin, the dielectric layer, and the etched back oxide layer; planarizing the metal oxide layer and the dielectric layer to expose the semiconductor fin; forming a gate structure extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and on opposite sides of the gate structure.