Abstract: A dual-band patch array antenna module and an electronic device using the same are provided. The dual-band patch array antenna module includes an insulative carrier substrate, a common conductive metal layer, a common grounding metal layer, an outer surrounding shielding structure, a plurality of first band antenna structures, and a plurality of second band antenna structures. The common conductive metal layer is disposed inside the insulative carrier substrate. The common grounding metal layer is disposed on the insulative carrier substrate. The outer surrounding shielding structure is electrically connected between the common conductive metal layer and the common grounding metal layer. Each first band antenna structure includes a first radiator, two first metal elements, two first feeding elements, and two first inner surrounding shielding assemblies.

Abstract: Provided is an electronic device for a temporal synchronization, which determines a set of parameters associated with each imaging device of a plurality of imaging devices. The set of parameters include frame rate of each imaging device. The electronic device generates a synchronization signal that includes a preamble pulse of a first time duration set based on the frame rate and a sequence of alternating ON and OFF pulses. Each pulse of the sequence of alternating ON and OFF pulses is of a second time duration set based on the set of parameters. Based on the synchronization signal, lighting devices may be controlled to generate a pattern of alternating light pulses that is captured by each imaging device. The electronic device further acquires a plurality of images that includes information about the pattern of alternating light pulses. The electronic device further synchronizes the plurality of images, based on the information.

Abstract: One wireless communication device includes a transmitter circuit and a control circuit, wherein the control circuit sets a request to send (RTS) frame, and controls the transmitter circuit to transmit the RTS frame via at least one channel excluding a preamble punctured channel. Another wireless communication device includes a transmitter circuit and a control circuit, wherein the control circuit sets an RTS frame, and controls the transmitter circuit to transmit the RTS frame via a plurality of channels including the preamble punctured channel.

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

Abstract: A data transmission system and method thereof for edge computing are provided. A terminal mobile station international subscriber directory number (MSISDN) and a terminal IP of a target terminal are obtained with a domain name system (DNS) by a device providing communication services from the data transmission system. After data packets are sent to the data transmission system, if the target terminal is in an idle mode, a paging message is sent by a terminal wake-up module to enable the target terminal to return to a connected mode for communication. Before a connection is established between the data transmission system and the target terminal, downlink data packets can be temporarily stored, and the packets can be sent after the target terminal is in the connected mode. A computer readable medium for executing the data transmission method is also provided.

Abstract: A multi-link device (MLD) includes a transmit (TX) circuit, a receive (RX) circuit, and a control circuit. The control circuit controls the RX circuit to receive a first frame under an operation mode parameter with a first setting, control the TX circuit to transmit a second frame responsive to the first frame under the operation mode parameter with the first setting, and after the second frame is transmitted, controls the RX circuit to receive at least one physical layer protocol data unit (PPDU) under the operation mode parameter with a second setting, wherein the second setting is different from the first setting. None of the first frame and the second frame carries indication of operation mode parameter change that specifies the use of the second setting, and the use of the second setting is indicated by transmission of the second frame.

Abstract: A method of forming a semiconductor device comprises forming a fin structure; forming a source/drain structure in the fin structure; and forming a gate electrode over the fin structure. The source/drain structure includes Si1?x?yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, 0.01?x?0.1, and 0.01?y?0.

Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.

Abstract: A method for optimizing image capture of a scene by a swarm of drones including a root drone and first and second level-1 drones involves the root drone following a predetermined trajectory over the scene, capturing one or more root keyframe images, at a corresponding one or more root drone orientations and root drone-to-scene distances. For each root keyframe image: the root drone generates a ground mask image for that root keyframe image, and applies that ground mask image to the root keyframe image to generate a target image. The root drone then analyzes the target image to generate first and second scanning tasks for the first and second level-1 drones to capture a plurality of images of the scene at a level-1 drone-to-scene distance smaller than the root drone-to-scene distance; and the first and second level-1 drones carry out the first and second scanning tasks respectively.

Abstract: A method of testing a non-volatile memory (NVM) array includes obtaining a current distribution of a subset of NVM cells of the NVM array, the current distribution including first and second portions corresponding to respective logically high and low states of the subset of NVM cells, programming an entirety of the NVM cells of the NVM array to one of the logically high or low states, determining an initial bit error rate (BER) by performing first and second pass/fail (P/F) tests on each NVM cell of the NVM array, and using the current distribution to adjust the initial BER rate. Each of obtaining the current distribution, programming the entirety of the NVM cells, and performing the first and second P/F tests is performed while the NVM array is heated to a target temperature.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a lead frame and a sub-substrate disposed on the lead frame, wherein the thickness of the sub-substrate is between 0 and 0.5 ?m. The semiconductor structure also includes an epitaxial layer disposed on the sub-substrate. The epitaxial layer includes a buffer layer, a channel layer and a barrier layer. The buffer layer is disposed between the sub-substrate and the channel layer. The channel layer is disposed between the buffer layer and the barrier layer. The semiconductor structure further includes a device layer disposed on the barrier layer and an interconnector structure electrically connected to the epitaxial layer and/or the device layer by a through hole.

Abstract: An overhead hoist transfer system and an overhead hoist transfer. The overhead hoist transfer system includes a plurality of lower rails, a plurality of upper rail sets, and a plurality of overhead hoist transfers. The overhead hoist transfer includes a moving kit and a frame. The moving kit includes a control module, a drive wheel set, and a plurality of upper guide wheels. The control module controls the upper guide wheels to move between an upper position and a lower position. Before the overhead hoist transfer makes a turn along the lower rail and the upper rail set, the control module controls the upper guide wheels to move to the upper position or the lower position. When the plurality of upper guide wheels abut against the adjacent upper rail set, the overhead hoist transfer turns along the upper rail set.

Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate While spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.

Abstract: In an embodiment, a method includes: receiving, within a processing chamber, a wafer with a photoresist mask above a metal layer, wherein the processing chamber is connected to a gas source; applying an etchant configured to etch the metal layer in accordance with the photoresist mask within the processing chamber; and applying gas from the gas source to perform plasma ashing in the processing chamber.

Abstract: A backlight module includes a light guide plate, a light source, multiple first optical microstructures, and multiple second optical microstructures. The first optical microstructures and the second optical microstructures are disposed on the bottom surface of the light guide plate. Each of the first optical microstructures has a first light receiving surface facing the light source. Each of the second optical microstructures has a second light receiving surface facing the light source. A first angle is included between the first light receiving surface and the bottom surface. A second angle is included between the second light receiving surface and the bottom surface. The second angle is different from the first angle. A display apparatus adopting the backlight module is also provided.

Abstract: Throughput is preserved in a distributed system while maintaining concurrency by pushing a commit wait period to client commit paths and to future readers. As opposed to servers performing commit waits, the servers assign timestamps, which are used to ensure that causality is preserved. When a server executes a transaction that writes data to a distributed database, the server acquires a user-level lock, and assigns the transaction a timestamp equal to a current time plus an interval corresponding to bounds of uncertainty of clocks in the distributed system. After assigning the timestamp, the server releases the user-level lock. Any client devices, before performing a read of the written data, must wait until the assigned timestamp is in the past.

Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions.

Abstract: The disclosure provides a power transmission system and method. The power transmission method includes: determining to perform a charging operation or a discharge operation between a battery module and a power supplying/receiving module according to a handshake procedure performed by a power transmission module. Performing the charging operation includes: adjusting a supply voltage outputted by the power supplying/receiving module; and converting the supply voltage into a charging voltage received by the battery module to charge the battery module. Performing the discharging operation includes: converting a discharge voltage outputted by the battery module into a required voltage required by the power supplying/receiving module to supply the power supplying/receiving module. The charging operation or the discharging operation is performed in a maximum power mode, an optimal efficiency mode or a combination thereof between the battery module and the power supplying/receiving module.

Abstract: A screw for particle board includes a head; a threaded shank; and a plurality of screw threads formed on the threaded shank. The head includes a slot on a top. The threaded shank is formed with the head and includes a shank and a tip at an end of the shank. The screw threads are formed on both the shank and the tip. The shank includes a plurality of longitudinal recesses and a plurality of longitudinal projections. Each recess is adjacent to each projection. Each screw thread is disposed between one of the recesses and the projection adjacent to the recess.

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.