Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes an image sensing element arranged within a substrate. One or more isolation structures are arranged within one or more trenches disposed on opposing sides of the image sensing element. The one or more isolation structures extend from a first surface of the substrate to within the substrate. The one or more isolation structures respectively include a reflective element configured to reflect electromagnetic radiation.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a bottom electrode via (BEVA) in a dielectric layer, a recap layer on the BEVA, a bottom electrode on the recap layer, and a magnetic tunneling junction (MTJ) layer over the recap layer and vertically aligning with the BEVA. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA and a copper layer over the lining layer, filling the trench of the BEVA. The copper layer has a dimpled structure with a top surface lower than a top surface of the dielectric layer. The recap layer overlaps a top surface of the lining layer, an entire top surface of the copper layer, and a portion of the dielectric stack adjacent to the lining layer.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) device. In some embodiments, the method may be performed by forming a first electrode structure over a substrate. A doped data storage element is formed over the first electrode structure. The doped data storage element is formed by forming a first data storage layer over the first electrode structure and forming a second data storage layer over the first data storage layer. The first data storage layer is formed to have a first doping concentration of a dopant and the second data storage layer is formed to have a second doping concentration of the dopant that is less than the first doping concentration. A second electrode structure is formed over the doped data storage element.

Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure. A top electrode overlies a bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The second data storage layer is disposed between the first and third data storage layers. The second data storage layer has a lower bandgap than the third data storage layer. The first data storage layer has a lower bandgap than the second data storage layer.

Abstract: A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.

Abstract: The present disclosure relates to a memory device. The memory device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes one or more metals having non-zero concentrations that change as a distance from the substrate increases.

Abstract: Various embodiments of the present application are directed towards an image sensor having a reflector. In some embodiments, the image sensor comprises a substrate, an interlayer dielectric (ILD) structure, an etch stop layer, a wire, and the reflector. The substrate comprises a photodetector. The ILD structure is over the substrate, and the etch stop layer is over the ILD structure. The wire is in the etch stop layer. The reflector is directly over the photodetector and is in the etch stop layer. An upper surface of the wire is elevated above an upper surface of the reflector. By forming the reflector directly over the photodetector, the reflector may reflect radiation that passes through the photodetector without being absorbed back to the photodetector. This gives the photodetector a second chance to absorb the radiation and enhances the quantum efficiency (QE) of the photodetector.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer over the lower electrode, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. Oxygen ions are bonded more tightly in the second dielectric layer than those in the first dielectric layer, and oxygen ions are bonded more tightly in the second dielectric layer than those in the third dielectric layer.

Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.

Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The structure also includes a resistance variable layer over the lower electrode and an ion diffusion barrier layer over the resistance variable layer. The structure further includes a capping layer over the ion diffusion barrier layer, and the capping layer is made of a metal material. In addition, the structure includes an upper electrode over the capping layer. The structure includes a protective element extending along a sidewall of the ion diffusion barrier layer and in direct contact with an interface between the resistance variable layer and the ion diffusion barrier layer.

Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.

Abstract: The present disclosure provides a photosensitive device. The photosensitive device includes a donor-intermix-acceptor (PIN) structure. The PIN structure includes an organic hole transport layer; an organic electron transport layer; and an intermix layer sandwiched between the hole transport organic material layer and the electron transport organic material layer. The intermix layer includes a mixture of an n-type organic material and a p-type organic material.

Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends along sidewalls of the bottom electrode, the switching dielectric, and the top electrode and an upper surface of a lower dielectric layer. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The the sidewall spacer layer separates the lower etch stop layer from the lower dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure has a plurality of sub-layers including one or more metals having non-zero concentrations that change as a distance from the first electrode increases.

Abstract: A structure and formation method of a semiconductor device structure is provided. The method includes forming a lower electrode layer over a semiconductor substrate and forming a data storage layer over the lower electrode layer. The method also includes forming an ion diffusion barrier layer over the data storage layer and forming a capping layer over the ion diffusion barrier layer. The ion diffusion barrier layer is a metal material doped with nitrogen, carbon, or a combination thereof. The capping layer is made of a metal material. The method further includes forming an upper electrode layer over the capping layer.

Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.