Abstract: A method for managing periodic packets, a server and a network equipment are provided. The method includes the steps of receiving at least one transmission parameter of a plurality of periodic packets, determining at least one time sequence for rearranging and transmitting the periodic packets according to the at least one transmission parameter, transmitting the at least one time sequence, and receiving and disassembling the periodic packets already rearranged and transmitted according to the at least one time sequence.

Abstract: The present disclosure provides a protective casing, configured for protecting an electronic device. The protective casing comprises an outer casing and an inner casing. The outer casing is made of metal material. The inner casing is positioned inside the outer casing. The inner casing is made of nonmetal material, and the inner casing is clipped with the outer casing.

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

Abstract: A method for managing periodic packets, a server and a network equipment are provided. The method includes the steps of receiving at least one transmission parameter of a plurality of periodic packets, determining at least one time sequence for rearranging and transmitting the periodic packets according to the at least one transmission parameter, transmitting the at least one time sequence, and receiving and disassembling the periodic packets already rearranged and transmitted according to the at least one time sequence.

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

Abstract: A multifunctional floating apparatus, which is able to float on water, includes a floating device, a handrail, a driving device, a controlling device, and a battery set. The floating device has an exterior edge and an interior edge, wherein the exterior edge is longer than the interior edge, and the floating device has an inner side at the interior edge. The handrail is connected to the inner side of the floating device, wherein the handrail has at least a holding portion for a user to hold the handrail. The driving device is provided on the floating device to drive the floating device to sail on water. The controlling device is electrically connected to the driving device to control the controlling device. The battery set is disposed to the floating device to supply the driving device with electric power.

Abstract: A connector is fixed in an opening of a housing of an electronic device. The connector comprises a main body housed in the opening, a gasket and a securing member. The main body comprises a plug portion, and an engaging portion connecting the plug portion. Furthermore, an engaging groove located on the engaging portion adjacent to the plug portion. The gasket located between the between the plug portion and the housing. The engaging portion sequentially passes through the gasket and the opening to make a part of the engaging groove away from the plug portion is located a side of the housing. The securing member partly engaged in the engaging groove and sandwiched between the engaging portion and the housing to fix the main body to the housing.

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region, forming first and second gate stacks over the first and second regions, respectively, the first and second gate stacks each including a dummy gate electrode, removing the dummy gate electrodes from the first and second gate stacks, respectively, thereby forming trenches, forming a metal layer to partially fill the trenches, forming an oxide layer over the metal layer filling a remaining portion of the trenches, applying a first treatment to the oxide layer, forming a patterned photoresist layer on the oxide layer overlying the first region, applying a second treatment to the oxide layer overlying the second region, etching the oxide layer overlying the second region, etching the first metal layer overlying the second region, removing the patterned photoresist layer, and removing the oxide layer overlying the first region.

Abstract: The preferred embodiment of the present invention provides a novel method of forming MOS devices using hydrogen annealing. The method includes providing a semiconductor substrate including a first region and a second region, forming at least a portion of a first MOS device covering at least a portion of the first active region, performing a hydrogen annealing in an ambient containing substantially pure hydrogen on the semiconductor substrate. The hydrogen annealing is performed after the step of the at least a portion of the first MOS device is formed, and preferably after a pre-oxidation cleaning. The method further includes forming a second MOS device in the second active region after hydrogen annealing. The hydrogen annealing causes the surface of the second active region to be substantially rounded, while the surface of the first active region is substantially flat.

Abstract: In one embodiment, a method of growing a heteroepitaxial layer comprises providing a patterned substrate containing patterned features having sidewalls. The method also includes directing ions toward the sidewalls in an exposure, wherein altered sidewall regions are formed, and depositing the heteroepitaxial layer under a set of deposition conditions effective to preferentially promote epitaxial growth on the sidewalls in comparison to other surfaces of the patterned features.

Abstract: A remote management system for Customer premises equipment WAN Management Protocol (CWMP) is provided. The remote management system includes at least one CPE (Customer Premises Equipment) and one server coupled to the CPE via a network. The CPE transmits a request to the server via the network. The server processes the request from the CPE according to a processing order, wherein the server provides a table which contains forecasted processing times for commands of a plurality of data models compatible with the CWMP. Upon receiving the request, the server generates a command configuration document according to the request, forecasts and obtains a first processing time corresponding to the command configuration document, and then dynamically adjusts and arranges the processing order for processing the request in the server according to the first processing time and a maximum waiting time corresponding to the request.

Abstract: A workpiece is implanted to a first depth to form a first amorphized region. This amorphized region is then etched to the first depth. After etching, the workpiece is implanted to a second depth to form a second amorphized region below a location of the first amorphized region. The second amorphized region is then etched to the second depth. The implant and etch steps may be repeated until structure is formed to the desired depth. The workpiece may be, for example, a compound semiconductor, such as GaN, a magnetic material, silicon, or other materials.

Abstract: A system and a method for transmitting network packets are provided. The system includes an information module, a scheduling module, and a forwarding module. The information module receives and records media information of a plurality of multimedia streams. The scheduling module calculates a guaranteed bit rate of each multimedia stream according to the media information provided by the information module, and rearranges isochronous packets of the multimedia streams in the first time slots of a plurality of clock cycles according to the guaranteed bit rates so that the transmission of the isochronous packets satisfies the guaranteed bit rates. The length of each clock cycle is a predetermined length. The length of the first time slot and the predetermined length are in a predetermined ratio. The forwarding module transmits all the packets of a clock cycle to a network at every a time interval of the predetermined length.

Abstract: An improved method of creating LED arrays is disclosed. A p-type layer, multi-quantum well and n-type layer are disposed on a substrate. The device is then etched to expose portions of the n-type layer. To create the necessary electrical isolation between adjacent LEDs, an ion implantation is performed to create a non-conductive implanted region. In some embodiments, an implanted region extends through the p-type layer, MQW and n-type layer. In another embodiment, a first implanted region is created in the n-type layer. In addition, a second implanted region is created in the p-type layer and multi-quantum well immediately adjacent to etched n-type layer. In some embodiments, the ion implantation is done perpendicular to the substrate. In other embodiments, the implant is performed at an angle.

Abstract: A multifunctional floating apparatus, which is able to float on water, includes a floating device, a handrail, a driving device, a controlling device, and a battery set. The floating device has an exterior edge and an interior edge, wherein the exterior edge is longer than the interior edge, and the floating device has an inner side at the interior edge. The handrail is connected to the inner side of the floating device, wherein the handrail has at least a holding portion for a user to hold the handrail. The driving device is provided on the floating device to drive the floating device to sail on water. The controlling device is electrically connected to the driving device to control the controlling device. The battery set is disposed to the floating device to supply the driving device with electric power.

Abstract: An improved method of fabricating a semiconductor light emitting diode (LED) is disclosed. The current blocking layer and the contact area for the n-type layer are implanted at the same time. In some embodiments, a dopant, which may be an n-type dopant, is implanted into a portion of the p-type layer to cause that portion to become either u-type or n-type. Simultaneously, the same dopant is implanted into at least a portion of the exposed n-type layer to increase its conductivity. After this implant, the dopant in both portions of the LED may be activated through the use of a single anneal cycle.

Abstract: An improved method of fabricating a vertical semiconductor LED is disclosed. Ions are implanted into the LED to create non-conductive regions, which facilitates current spreading in the device. In some embodiments, the non-conductive regions are located in the p-type layer. In other embodiments, the non-conductive layer may be in the multi-quantum well or n-type layer.

Abstract: A lateral light emitting diode comprises a layer stack disposed on one side of a substrate, the layer stack including a p-type layer, n-type layer, and a p/n junction formed therebetween. The LED may further include a p-electrode disposed on a first side of the substrate and being in contact with the p-type layer on an exposed surface and an n-electrode disposed on the first side of the substrate and being in contact with an exposed surface of an n+ sub-layer of the n-type layer.

Abstract: An improved method of fabricating a semiconductor light emitting diode (LED) is disclosed. The current blocking layer and the contact area for the n-type layer are implanted at the same time. In some embodiments, a dopant, which may be an n-type dopant, is implanted into a portion of the p-type layer to cause that portion to become either u-type or n-type. Simultaneously, the same dopant is implanted into at least a portion of the exposed n-type layer to increase its conductivity. After this implant, the dopant in both portions of the LED may be activated through the use of a single anneal cycle.