Abstract: The present invention is to provide a method for enabling a tracker/coordinator in a P2P system to receive server address queries from network devices through Internet; provide address of a protocol server to the network devices according to the server address queries, so as for the network devices to conduct NAT behavior tests on NAT routers connected therewith through the protocol server; assigning a first network device with the router incapable of forwarding messages to a second network device with the router capable of forwarding messages according to the test results; providing a mapped address of a port of the second network device to a third network device, when receiving a port query from the third network device and determining that the port query corresponds to the first network device, so as for the third network device to directly connect with the first network device through the second network device.

Abstract: A display panel includes a first substrate, and at least one data driver integrated circuit. The data driver integrated circuit is electrically connected to the first substrate, wherein the data driver integrated circuit receives a first set signal and a second set signal, the first set signal includes a first data transmission interface, the second set signal includes a second data transmission interface, and the first data transmission interface and the second data transmission interface are different.

Abstract: An apparatus of digital phase lock loop and method are provided. In one embodiment, an apparatus comprises: an analog-to-digital converter (ADC) for converting a voltage level of an output clock into a first digital word in accordance with a timing defined by a reference clock; a first digital loop filter for receiving the first digital word and outputting a control code; a circuit to receive the reference clock and the output clock and output an offset code according to a frequency error of the output clock with respect to a frequency of the reference clock; an adder for generating an offset control code by summing the control code with the offset code; and a digitally controlled oscillator for outputting the output clock in accordance with the offset control code.

Abstract: The session-aware NAT traversal method is used to establish network communication between two hosts, wherein a first and a second host are located behind a first and a second NAT router, respectively. First, these hosts conduct a standard NAT traversal to establish a session. Then, the second host sends a registration request message to the first NAT router for session registration. Upon receiving the registration request message, the first NAT router generates a session ID for this session and replies to the second host. As the second host moves to a private network behind a third NAT router, the second host only needs to send a new registration request message with the session ID to the first NAT router. The first NAT router observes a new mapped address of the second host and allows inbound traffic from the new mapped address without further NAT traversal.

Abstract: The present invention is to provide a network system, which comprises a coordinator server located in a public network; first and second NATs (Network Address Translators) located in first and second private networks and configured as a full-cone NAT, respectively; first and second network devices located in the first and second private networks and connected to the public network through the first and second NATs, respectively, wherein each of the first and second network devices has registered two mapped addresses with the coordinator server, respectively; a third NAT located in a third private network; and a third network device located in the third private network and connected to the public network through the third NAT, wherein the third network device can obtain the mapped addresses from the coordinator server and, based on the mapped addresses, conduct NAT behavior tests on the third NAT through the first and second network devices.

Abstract: In an embodiment, a receiver comprises: a linear equalizer for receiving an input signal and outputting a partly equalized signal; a VGA (variable-gain amplifier) for receiving the partly equalized signal and outputting an amplitude-adjusted signal in accordance with a gain control signal; a non-uniform ADC (analog-to-digital converter) for receiving the amplitude-adjusted signal and outputting a digitized signal; and a DSP (digital signal processing) circuit for receiving the digitized signal and outputting a bit stream by performing a signal detection and establishing the gain control signal by performing an amplitude comparison. The non-uniform ADC has a lower precision when the amplitude-adjusted signal lies in a region where the signal detection is of a higher confidence, and has a higher precision when the amplitude-adjusted signal lies in a region where the signal detection is of a lower confidence. In an embodiment, the DSP circuit includes a decision feedback equalizer.

Abstract: A filter of an adjustable frequency response comprises a plurality of filters having a plurality of distinct frequency responses, respectively. These filters receive a common input signal and generate a plurality of intermediate signals, respectively. A multiplexing circuit is used to select one of these intermediate signals as a filtered signal. The multiplexing circuit is controlled by a control signal that is related to a state of the filtered signal.

Abstract: A serial data link receiver and method are provided. In one implementation, the receiver includes a first equalizer for receiving a first received signal and outputting a first equalized signal, and a second equalizer for receiving a second received signal and outputting a second equalized signal. The receiver further includes an analog CDR (clock-data recovery) circuit for receiving the first equalized signal and outputting a first recovered bit stream and a first recovered clock generated in accordance with an analog control voltage, and a digital CDR circuit for receiving the second equalized signal and the first recovered clock and outputting a second recovered bit stream and a second recovered clock based on selecting a phase of the first recovered clock in accordance with a digital phase selection signal.

Abstract: In an embodiment, a receiver comprises: a linear equalizer for receiving an input signal and outputting a partly equalized signal; a VGA (variable-gain amplifier) for receiving the partly equalized signal and outputting an amplitude-adjusted signal in accordance with a gain control signal; a non-uniform ADC (analog-to-digital converter) for receiving the amplitude-adjusted signal and outputting a digitized signal; and a DSP (digital signal processing) circuit for receiving the digitized signal and outputting a bit stream by performing a signal detection and establishing the gain control signal by performing an amplitude comparison. The non-uniform ADC has a lower precision when the amplitude-adjusted signal lies in a region where the signal detection is of a higher confidence, and has a higher precision when the amplitude-adjusted signal lies in a region where the signal detection is of a lower confidence. In an embodiment, the DSP circuit includes a decision feedback equalizer.

Abstract: In one embodiment, an apparatus comprises: an MRAM (magnetic random access memory) cell array comprising a plurality of MRAM cells including a calibration cell and a plurality of data cells; a reference MRAM cell controlled by a control signal; and a sensing-amplifier/latch; wherein: said plurality of data cells are used for storing user data; the calibration cell is used for a calibration purpose; the reference MRAM cell serves as a reference for comparison with a MRAM cell selected within the MRAM cell array; the sensing-amplifier/latch outputs a logical signal based on comparing a resistance of the MRAM cell selected within the MRAM cell array and a resistance of the reference MRAM cell; and the control signal is established in a calibration process by comparing a resistance of the calibration cell with the resistance of the reference MRAM cell.

Abstract: In one embodiment, an apparatus comprises: an MRAM (magnetic random access memory) cell array comprising a plurality of MRAM cells including a calibration cell and a plurality of data cells; a reference MRAM cell controlled by a control signal; and a sensing-amplifier/latch; wherein: said plurality of data cells are used for storing user data; the calibration cell is used for a calibration purpose; the reference MRAM cell serves as a reference for comparison with a MRAM cell selected within the MRAM cell array; the sensing-amplifier/latch outputs a logical signal based on comparing a resistance of the MRAM cell selected within the MRAM cell array and a resistance of the reference MRAM cell; and the control signal is established in a calibration process by comparing a resistance of the calibration cell with the resistance of the reference MRAM cell.

Abstract: A main ADC (analog-to-digital converter) for converting an analog input signal into a digital data, and an auxiliary ADC for converting the same analog input signal into an auxiliary digital data, wherein: the main ADC is a successive-approximation-register (SAR) ADC of a first resolution with a first conversion speed; the auxiliary ADC is of a second resolution with a second conversion speed; the second resolution is lower than the first resolution but the second conversion speed is higher than the first conversion speed; and the main ADC generates the digital data by undergoing a process of successive approximation comprising a plurality of steps including a fast-track step that is based on a value of the auxiliary digital data.

Abstract: A method for generating an output clock comprising: detecting a timing difference between a first input clock and a second input clock to generate a phase error signal; generating a masked phase error signal by masking the phase error signal based on a deterministic jitter indicator signal; generating an oscillator control signal by filtering the masked phase error signal; and generating the output clock in accordance with the oscillator control signal.

Abstract: An integrated switch-capacitor DC-DC converter and method are disclosed. In an embodiment, a converter includes a switch-capacitor network for receiving a source voltage and outputting a load voltage to a load circuit in accordance with a N-bit control code and a plurality of phase clocks, wherein N is an integer greater than 1, a load capacitor for holding the load voltage, a feedback network for generating a feedback voltage proportional to the load voltage, and a controller for receiving the feedback voltage and a reference voltage and outputting the N-bit control code in accordance with a clock phase of the plurality of phase clocks.

Abstract: A method for generating an output clock comprising: detecting a timing difference between a first input clock and a second input clock to generate a phase error signal; generating a masked phase error signal by masking the phase error signal based on a deterministic jitter indicator signal; generating an oscillator control signal by filtering the masked phase error signal; and generating the output clock in accordance with the oscillator control signal.

Abstract: An integrated switch-capacitor DC-DC converter and method are disclosed. In an embodiment, a converter includes a switch-capacitor network for receiving a source voltage and outputting a load voltage to a load circuit in accordance with a N-bit control code and a plurality of phase clocks, wherein N is an integer greater than 1, a load capacitor for holding the load voltage, a feedback network for generating a feedback voltage proportional to the load voltage, and a controller for receiving the feedback voltage and a reference voltage and outputting the N-bit control code in accordance with a clock phase of the plurality of phase clocks.

Abstract: The present invention discloses an integrated storage platform system and a method thereof. The system comprises at least one adaption module respectively connecting with at least one storage space and each performing a plurality of adaption settings corresponding to one storage space; a storage administration module connecting with the adaption modules and processing the files of the storage spaces; and an access interface connecting the storage administration module, operated by a user to access the storage space through the storage administration module and the adaption module, and presenting access results to the user. The present invention establishes different adaption modules to enable the user to link to and access different types of storage spaces.

Abstract: The present invention is to provide a network system, which comprises a coordinator server located in a public network; first and second NATs (Network Address Translators) located in first and second private networks and configured as a full-cone NAT, respectively; first and second network devices located in the first and second private networks and connected to the public network through the first and second NATs, respectively, wherein each of the first and second network devices has registered two mapped addresses with the coordinator server, respectively; a third NAT located in a third private network; and a third network device located in the third private network and connected to the public network through the third NAT, wherein the third network device can obtain the mapped addresses from the coordinator server and, based on the mapped addresses, conduct NAT behavior tests on the third NAT through the first and second network devices.

Abstract: The present invention is to provide a method for enabling a tracker/coordinator in a P2P system to receive server address queries from network devices through Internet; provide address of a protocol server to the network devices according to the server address queries, so as for the network devices to conduct NAT behavior tests on NAT routers connected therewith through the protocol server; assigning a first network device with the router incapable of forwarding messages to a second network device with the router capable of forwarding messages according to the test results; providing a mapped address of a port of the second network device to a third network device, when receiving a port query from the third network device and determining that the port query corresponds to the first network device, so as for the third network device to directly connect with the first network device through the second network device.

Abstract: A signal level detector and detecting method are provided. In one implementation a method includes receiving a differential input signal; incorporating two configurable rectifiers of the same circuit topology; configuring a first one of the two configurable rectifiers as a inverting rectifier to generate an inverting end of an output signal in response to an absolute value of the differential input signal; and configuring a second one of the two configurable rectifiers as a non-inverting rectifier to generate a non-inverting end of the output signal.