Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

Abstract: Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit. Additional methods are disclosed.

Abstract: A method for forming a pellicle apparatus involves forming a device substrate by depositing one or more pellicle layers defined over a base device layer, where a release layer is formed thereover. An adhesive layer is formed over a transparent carrier substrate. The adhesive layer is bonded to the release layer, defining a composite substrate comprised of the device and carrier substrates. The base device layer is removed from the composite structure and a pellicle frame is attached to an outermost one of the pellicle layers. A pellicle region is isolated from a remainder of the composite structure, and an ablation of the release layer is performed through the transparent carrier substrate, defining the pellicle apparatus comprising a pellicle film attached to the pellicle frame. The pellicle apparatus is then from a remaining portion of the composite substrate.

Abstract: A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

Abstract: An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.

Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.

Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode over a substrate. A data storage layer is over the bottom electrode and has a first thickness. A capping layer is over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 1.9 and approximately 3 times thicker than the first thickness. A top electrode is over the capping layer.

Abstract: The present disclosure relates to a method of forming a MIM (metal-insulator-metal) capacitor using a post capacitor bottom metal (CBM) treatment process to reduce a roughness of a top surface of a capacitor bottom metal layer, and an associated apparatus. In some embodiments, the method is performed by forming a capacitor bottom metal layer having a first metal material over a semiconductor substrate. A top surface of the capacitor bottom metal layer is exposed to one or more post CBM treatment agents having oxygen. The one or more post CBM treatment agents reduce a roughness of the top surface and form an interface layer having the first metal material and oxygen onto and in direct contact with the top surface of the capacitor bottom metal layer. A capacitor dielectric layer is formed over the interface layer and a capacitor top metal layer is formed over the capacitor dielectric layer.

Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a tunnel oxide is formed over a semiconductor substrate. A layer of silicon dot nucleates is formed on the tunnel oxide. The layer of silicon dots includes silicon dot nucleates having respective initial sizes which differ according to a first size distribution. An etching process is performed to reduce the initial sizes of the silicon dot nucleates so reduced-size silicon dot nucleates have respective reduced sizes which differ according to a second size distribution. The second size distribution has a smaller spread than the first size distribution.

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.

Abstract: A semiconductor device includes a substrate, and a seed layer over the substrate, wherein the seed layer comprises carbon dopants. The semiconductor device further includes a channel layer over the seed layer, and an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A method of making a transistor includes forming a seed layer over a substrate, and doping the seed layer, wherein doping the seed layer comprises introducing carbon dopants into the seed layer. The method further includes forming a channel layer over the seed layer, and forming an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first gate electrode formed over the substrate. The semiconductor structure further includes a dielectric layer formed on a sidewall of the first gate electrode and a second gate electrode formed over the substrate and separated from the first gate electrode by the dielectric layer. The semiconductor structure further includes a contact formed over the second gate electrode. In addition, the contact has a first extending portion and a second extending portion extending along opposite sidewalls of the second gate electrode.

Abstract: An exemplary method includes forming a common source region in a substrate, and forming an isolation feature over the common source region. The common source region is disposed between the substrate and the isolation feature. The common source region and the isolation feature span a plurality of active regions of the substrate. A gate, such as an erase gate, may be formed after forming the common source region. In some implementations, the common source region is formed by etching the substrate to form a saw-tooth shaped recess region (or a U-shaped recess region) and performing an ion implantation process to form a doped region in a portion of the saw-tooth shaped recess region (or the U-shaped recess region), such that the common source region has a sawtooth profile (or a U-shaped profile).

Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.

Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer; receiving a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer; bonding the first dielectric layer with the second dielectric layer; and bonding the first conductive structure with the second conductive structure.

Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode disposed over a lower interconnect layer and a data storage layer having a first thickness over the bottom electrode. A capping layer is disposed over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 and approximately 3 times thicker than the first thickness. A top electrode is disposed over the capping layer and an upper interconnect layer is disposed over the top electrode.