Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate structure over a substrate and laterally surrounded by a first sidewall spacer. The first gate structure protrudes outward from a top of the first sidewall spacer. A second gate structure is over the substrate and is laterally surrounded by a second sidewall spacer. The first gate structure has a first height that is larger than a second height of the second gate structure. The first sidewall spacer has a first cross-sectional profile that is a different shape and a different size than a second cross-sectional profile of the second sidewall spacer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip having a flash gate structure disposed over a substrate and including a control gate separated from a floating gate by an inter-electrode dielectric. One or more first sidewall spacers laterally surround the flash gate structure. The inter-electrode dielectric is directly between the one or more first sidewall spacers. A logic gate structure is disposed over the substrate and is laterally surrounded by one or more second sidewall spacers having a smaller height than the one or more first sidewall spacers.

Abstract: A method for forming a semiconductor is provided. The method includes etching a trench in a semiconductor substrate, in which the trench surrounds a device region of the semiconductor substrate; forming a conductive feature in the trench; and forming a transistor on the device region of the semiconductor substrate after forming the conductive feature.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Abstract: A method for identifying a foreground object in an image and an electronic device are provided. The method includes: dividing a first image and a second image to obtain first image blocks in the first image and second image blocks in the second image; comparing the first image blocks with the second image blocks to obtain a plurality of disparity values respectively corresponding to the first image blocks, and generating a disparity image including the disparity values; comparing each disparity value in the disparity image with a first threshold to form a disparity depth image, and selecting a selected block from the disparity depth image to form a first region; and mapping the first region into the first image to identify a mapped object and identify the object as a foreground object.

Abstract: A gesture recognition method and a gesture recognition device are provided. The gesture recognition method includes the steps of: obtaining a hand image including a gesture graphic; determining a reference point in the gesture graphic; determining circular arc reference lines by using the reference point as a center; determining intersection points of each of the circular arc reference lines intersecting with a boundary of the gesture graphic; determining whether at least two finger blocks of a plurality of finger blocks of the gesture graphic conform to an approaching trend according to the circular arc reference lines and the intersection points, and determining whether the at least two finger blocks in a selected range of the gesture graphic forms a continuous graphic block; and when the at least two finger blocks of the gesture graphic conform to the approaching trend and form the continuous graphic block, determining the hand image as a hand pinch image.

Abstract: A gesture recognition method includes performing a binarization process on an image to obtain a binarized image, wherein the binarized image includes a plurality of foreground pixels and a plurality of background pixels; determining whether the plurality of foreground pixels surrounds at least a first background pixel; and determining a gesture complying with a predefined gesture in response to determination that the plurality of foreground pixels surrounds the at least a first background pixel.

Abstract: A gesture recognition method and a gesture recognition device are provided. The gesture recognition method includes the steps of: obtaining a hand image including a gesture graphic; determining a reference point in the gesture graphic; determining circular arc reference lines by using the reference point as a center; determining intersection points of each of the circular arc reference lines intersecting with a boundary of the gesture graphic; determining whether at least two finger blocks of a plurality of finger blocks of the gesture graphic conform to an approaching trend according to the circular arc reference lines and the intersection points, and determining whether the at least two finger blocks in a selected range of the gesture graphic forms a continuous graphic block; and when the at least two finger blocks of the gesture graphic conform to the approaching trend and form the continuous graphic block, determining the hand image as a hand pinch image.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip having a flash gate structure disposed over a substrate and including a control gate separated from a floating gate by an inter-electrode dielectric. One or more first sidewall spacers laterally surround the flash gate structure. The inter-electrode dielectric is directly between the one or more first sidewall spacers. A logic gate structure is disposed over the substrate and is laterally surrounded by one or more second sidewall spacers having a smaller height than the one or more first sidewall spacers.

Abstract: A method for identifying a foreground object in an image and an electronic device are provided. The method includes: dividing a first image and a second image to obtain first image blocks in the first image and second image blocks in the second image; comparing the first image blocks with the second image blocks to obtain a plurality of disparity values respectively corresponding to the first image blocks, and generating a disparity image including the disparity values; comparing each disparity value in the disparity image with a first threshold to form a disparity depth image, and selecting a selected block from the disparity depth image to form a first region; and mapping the first region into the first image to identify a mapped object and identify the object as a foreground object.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate disposed over a substrate and having a first height measured between an upper surface of the substrate and a first uppermost surface of the first gate structure. A second gate structure is disposed over the substrate and has a second height measured between the upper surface of the substrate and a second uppermost surface of the second gate structure. The second height is smaller than the first height. A first sidewall spacer laterally surrounds the first gate structure and is recessed below the first uppermost surface. A second sidewall spacer laterally surrounds the second gate structure. A top of the first sidewall spacer is arranged along a horizontal plane that is vertically between the first uppermost surface and the second uppermost surface.

Abstract: A gesture recognition method includes performing a binarization process on an image to obtain a binarized image, wherein the binarized image includes a plurality of foreground pixels and a plurality of background pixels; determining whether the plurality of foreground pixels surrounds at least a first background pixel; and determining a gesture complying with a predefined gesture in response to determination that the plurality of foreground pixels surrounds the at least a first background pixel.

Abstract: A touch input system includes a touch surface, a reflective structure, and a touch-position generating device. The reflective structure is disposed to surround the touch surface and protrude out the touch surface. The touch-position generating device includes a pen-like body, a lighting and receiving module disposed in the pen-like body, and a processing module. The lighting and receiving module and the processing module are connected in communication. When the touch input system is in operation, the lighting and receiving module emits light toward the reflective structure and receives the light that is reflected by the reflective structure relative to the touch surface. Then, the processing module determines a touch position of the pen-like body on the touch surface according to the received light. Thereby, the touch-position generating device can perform the determination of the touch position independently from the operation of a touch panel or device providing the touch surface.

Abstract: A video editing method, a video editing device, and a video editing system are provided. A target is obtained from an original video. Relative position relations respectively between each frame and a previous frame and a next frame adjacent to it are obtained based on multiple image feature points of each frame. An adjustment process is executed respectively for each frame. The adjustment process includes: obtaining a frame N; identifying the target in the frame N; adjusting the frame N to obtain a new frame, wherein the target is located on a center of the new frame; and modifying the new frame based on the relative position relations to obtain a postproduction frame. A processed video is outputted based on multiple postproduction frames.

Abstract: The present disclosure relates to a method of forming sidewall spacers configured to improve dielectric fill between adjacent gate structures. In some embodiments, the method may be performed by depositing a sidewall spacer material over a first gate structure and a second gate structure. A first etching process is performed on the sidewall spacer material to form a first intermediate sidewall spacer surrounding the first gate structure and a second sidewall spacer surrounding the second gate structure. A masking material is formed over the substrate. Parts of the first intermediate sidewall spacer protrude outward from the masking material, while the second sidewall spacer is completely covered by the masking material. A second etching process is then performed on the parts of the first intermediate sidewall spacer protruding outward from the masking material to form a first sidewall spacer recessed below an uppermost surface of the first gate structure.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate disposed over a substrate and having a first height measured between an upper surface of the substrate and a first uppermost surface of the first gate structure. A second gate structure is disposed over the substrate and has a second height measured between the upper surface of the substrate and a second uppermost surface of the second gate structure. The second height is smaller than the first height. A first sidewall spacer laterally surrounds the first gate structure and is recessed below the first uppermost surface. A second sidewall spacer laterally surrounds the second gate structure. A top of the first sidewall spacer is arranged along a horizontal plane that is vertically between the first uppermost surface and the second uppermost surface.

Abstract: A video editing method, a video editing device, and a video editing system are provided. A target is obtained from an original video. Relative position relations respectively between each frame and a previous frame and a next frame adjacent to it are obtained based on multiple image feature points of each frame. An adjustment process is executed respectively for each frame. The adjustment process includes: obtaining a frame N; identifying the target in the frame N; adjusting the frame N to obtain a new frame, wherein the target is located on a center of the new frame; and modifying the new frame based on the relative position relations to obtain a postproduction frame. A processed video is outputted based on multiple postproduction frames.

Abstract: The present disclosure relates to a method of forming sidewall spacers configured to improve dielectric fill between adjacent gate structures. In some embodiments, the method may be performed by depositing a sidewall spacer material over a first gate structure and a second gate structure. A first etching process is performed on the sidewall spacer material to form a first intermediate sidewall spacer surrounding the first gate structure and a second sidewall spacer surrounding the second gate structure. A masking material is formed over the substrate. Parts of the first intermediate sidewall spacer protrude outward from the masking material, while the second sidewall spacer is completely covered by the masking material. A second etching process is then performed on the parts of the first intermediate sidewall spacer protruding outward from the masking material to form a first sidewall spacer recessed below an uppermost surface of the first gate structure.