Abstract: A control device is provided, in which the control device is coupled to an external memory and includes a storage circuit, a memory mapping circuit, and a central processing unit (CPU). The storage circuit stores a firmware image. The memory mapping circuit divides the firmware image into a plurality of segments and calculates the start address of each of the segments and the identifier code to generate an access sequence. The CPU reads the storage circuit and outputs the segments to the external memory according to the access sequence.

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, semiconductor dies over the interposer substrate, and an underfill element over the interposer substrate and between the semiconductor dies and interposer substrate. The semiconductor die package also includes a ring structure and one or more lid structures separated from the ring structure. The ring structure is coupled to the package substrate to control warpage. The lid structures are coupled to the top surfaces of the semiconductor dies to control warpage and help heat dissipation. In addition, the lid structures define a gap to allow a portion of the underfill element between the adjacent semiconductor dies to be exposed, so that stress concentration on that portion can be avoided or reduced. Accordingly, the reliability of the semiconductor die package is improved.

Abstract: A manufacturing method of a halogen-free flame-retardant thermoplastic braided fiber reinforced polymer composite board, comprising steps of: preparing a recycled material containing a halogen-free flame-retardant thermoplastic braided fiber reinforced polymer composite; adding a polymer base material to the recycled material to form a core layer material and extruding the core layer material with a low shear extruder; hot pressing the core layer material by rollers to obtain a recycled fiber core layer; preparing a reinforcement layer containing a fiber material or a fabric with pores; and stacking and hot pressing the recycled fiber core layer and the reinforcement layer.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first source/drain region, a second source/drain region, first source/drain contact and a first dielectric spacer liner. The gate structure is over the semiconductor substrate. The first source/drain region and the second source/drain region are in the semiconductor substrate and respectively on opposite sides of the gate structure. The first source/drain contact is over the first source/drain region. The first dielectric spacer liner lines a sidewall of the first source/drain contact and extends into the first source/drain region.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: In some embodiments, an electronic device displays a plurality of content items in a messaging conversation. In some embodiments, the electronic device displays user interfaces associated with one or more content items in a messaging conversation.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a dielectric structure over the substrate. The semiconductor device structure includes a contact structure passing through the dielectric structure. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer. The first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, the contact layer passes through the first barrier layer and extends into the dielectric structure, and the first barrier layer passes through the second barrier layer and extends into the dielectric structure.

Abstract: The present disclosure generally relates to providing indicators of distance. For example, display of a visual distance indicator that indicates the distance between a computer system and an entity is provided.

Abstract: A receiving box for two hearing assistance devices including a housing, a cover, and an L-shaped hinge is provided. The housing includes a hinge recess, and two receiving slots independent of each other. The two receiving slots are configured to respectively receive the hearing assistance devices. The L-shaped hinge includes two opposite ends. One end is pivoted in the hinge recess, and the other end is fixed to the cover.

Abstract: The present invention provides a wireless device including a first wireless module and a second wireless module is disclosed. The first wireless module is configured to transmit data periodically, the second wireless module is configured to communicate with an electronic device, and the second wireless module and the first wireless module perform data transmission/reception based on a time-division multiplexing method. In addition, the second wireless module determines a wake interval and a doze interval based on traffic characteristics of the first wireless module.

Abstract: The present disclosure provides a charging gun including a cable, an outer casing and a strain relief structure. The outer casing includes a first case and a second case, wherein the first case is detachably assembled with the second case. The strain relief structure includes a first portion, a second portion and a plurality of first ring-shaped protrusions. The first portion is detachably assembled with the second portion, the first portion is disposed on the first housing, and the second portion is disposed on the second housing. When the first case is assembled and connected with the second case, the first portion is assembled and connected with the second portion, and at least a part of a surface of the cable is covered by the strain relief structure, and the strain relief structure is clamped between the cable and the outer casing.

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

Abstract: A head of a tag device having a body, at least one row of negative-pressure through holes and at least one row of positive-pressure through holes. The body has a first surface and a second surface. The rows of negative and positive-pressure through holes are formed through the first and second surfaces of the body and arranged along a long-axis direction. Two negative and positive-pressure through holes at both ends of the corresponding row of negative and positive-pressure through holes are respectively close to the short sides of the body. Therefore, an effective labeling area is distributed between two short sides. The head of the tag device of the present invention provides a stable labeling operation for different products where different components are mounted and increases units per hour (UPH).

Abstract: A cable clamping assembly includes a cable clamp and a supporting base. The cable clamp includes a protruding base and two bendable arms. The protruding base has an opening disposed on the center of a top surface. The two bendable arms respectively include a plurality of first latching components and a plurality of second latching components. The supporting base includes a concave portion. A guiding slope and a positioning portion are disposed within the concave portion. When the cable clamp clamps a cable, the two bendable arms respectively slide downwardly along two ends of the guiding slope to surround the cable, until one of the two bendable arms is stopped by the positioning portion. The protruding base is deformed in response to a pressing force, so that the bendable arms tie the cable closely, and the plurality of first latching components lock with the plurality of second latching components.

Abstract: A semiconductor package includes a redistribution structure, a first conductive pillar and a second conductive pillar, and a semiconductor device. The redistribution structure has a first surface and a second surface opposite to the first surface. The first conductive pillar and the second conductive pillar are disposed on the first surface of the redistribution structure and electrically connected with the redistribution structure, wherein a maximum lateral dimension of the first conductive pillar is greater than a maximum lateral dimension of the second conductive pillar, and a topography variation of a top surface of the first conductive pillar is greater than a topography variation of a top surface of the second conductive pillar.

Abstract: The present invention provides multispecific antigen-binding molecules that bind both a T-cell antigen (e.g., CD3) and a target antigen (e.g., a tumor associated antigen, a viral or bacterial antigen), and which include a single polypeptide chain that is multivalent (e.g., bivalent) with respect to T-cell antigen binding, and uses thereof.

Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate. The chip structure has an inclined sidewall, the inclined sidewall is at an acute angle to a vertical, the vertical is a direction perpendicular to a main surface of the chip structure, and the acute angle is in a range from about 12 degrees to about 45 degrees. The method also includes forming a protective layer to surround the chip structure.

Abstract: A method for forming a chip package structure is provided. The method includes removing a first portion of a substrate to form a first recess in the substrate. The method includes forming a buffer structure in the first recess. A first Young's modulus of the buffer structure is less than a second Young's modulus of the substrate. The method includes forming a first wiring structure over the buffer structure and the substrate. The method includes bonding a chip package to the first wiring structure. The chip package has an interposer substrate and a chip structure over the interposer substrate, and a first corner of the interposer substrate and a second corner of the chip structure overlap the buffer structure in a top view of the chip package and the buffer structure.

Abstract: A semiconductor package includes a substrate, a first semiconductor device disposed over the substrate in an offset position toward an edge of the substrate, and a ring structure disposed over the substrate and surrounding the first semiconductor device. The ring structure includes an overhang portion cantilevered over the edge of the substrate.