Patents by Inventor Chia Ying Lee

Chia Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Double patterning method
    Patent number: 9711372
    Abstract: In some embodiments, the disclosure relates to a method of forming an integrated circuit device. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions. A mandrel is formed over the first mask layer and the cut regions, and the first mask layer is etched using the mandrel form a patterned first mask. The substrate is etched according to the patterned first mask and the cut regions to form trenches in the substrate, and the trenches are filled with conductive metal to form conductive lines.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Method of Fine Line Space Resolution Lithography For Integrated Circuit Features Using Double Patterning Technology
    Publication number: 20170194198
    Abstract: A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.
    Type: Application
    Filed: March 21, 2017
    Publication date: July 6, 2017
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Cut first self-aligned litho-etch patterning
    Patent number: 9698016
    Abstract: The present disclosure relates to a method for performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a first cut layer over a hard mask having a first layer and an underlying second layer. A first plurality of openings are formed within the first layer and expose the second layer at a first plurality of positions. Two or more of the first plurality of openings are separated by the first cut layer. A spacer material is selectively formed onto sidewalls of the first plurality of openings within the first layer. A second plurality of openings are then formed within the first layer. The second plurality of openings are separated by a second cut layer including the spacer material and expose the second layer at a second plurality of positions. The second layer is etched according to the first layer and the spacer material.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Nano Wire Structure and Method for Fabricating the Same
    Publication number: 20170154824
    Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.
    Type: Application
    Filed: February 10, 2017
    Publication date: June 1, 2017
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • PROCESSES FOR PREPARING BREXPIPRAZOLE
    Publication number: 20170145001
    Abstract: The present disclosure provides processes for preparing brexpiprazole. The present disclosure also provides processes for the purification of brexpiprazole. The processes for preparing and purifying brexpiprazole of the present invention provide substantial improvements over currently known methods. In certain embodiments, the conversion of Formula XI and XII to form XIII provides increased selectivity over previously reported methods. This offers increased yield and purity. The improved process for purifying brexpiprazole disclosed herein provides brexpiprazole with superior purity and is also more suitable for industrial production.
    Type: Application
    Filed: November 1, 2016
    Publication date: May 25, 2017
    Inventors: Chia-Ying LEE, Shu Ting HUANG, Hsin-Chi WANG, Yuan-Xiu LIAO, Jiunn-Cheh GUO, Lung-Huang KUO
  • Self-aligned nanowire formation using double patterning
    Patent number: 9633907
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Fine line space resolution lithography structure for integrated circuit features using double patterning technology
    Patent number: 9613903
    Abstract: A hard mask is disposed over a base material, and an I-shaped first opening is disposed in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Method of forming pattern for semiconductor device
    Patent number: 9601344
    Abstract: The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ying Lee, Chih-Yuan Ting, Jyu-Horng Shieh, Ming-Hsing Tsai, Syun-Ming Jang
  • Spacer Etching Process for Integrated Circuit Design
    Publication number: 20170069505
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 9, 2017
    Inventors: RU-GUN LIU, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHIH-MING LAI, CHIA-YING LEE, JYU-HORNG SHIEH, KEN-HSIEN HSIEH, MING-FENG SHIEH, SHAU-LIN SHUE, SHIH-MING CHANG, TIEN-I BAO, TSAI-SHENG GAU
  • Nano wire structure and method for fabricating the same
    Patent number: 9570358
    Abstract: A method comprises applying a first patterning process to a first photoresist layer to form a first opening, a second opening, a third opening and a fourth opening in the sacrificial layer, applying a second patterning process to a second photoresist layer to form a fifth opening, a sixth opening, a seventh opening and an eighth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the first and second patterning processes are substantially equal to each other, applying a third patterning process to a third photoresist layer to form a ninth opening, a tenth opening, an eleventh opening and a twelfth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the second and third patterning processes are substantially equal to each other and forming a plurality of nanowires based on the openings.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Method for forming line end space structure using trimmed photo resist
    Patent number: 9564327
    Abstract: One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: February 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai, Ken-Hsien Hsieh, Ru-Gun Liu
  • Voltage-enhanced energy storage devices
    Patent number: 9559386
    Abstract: The present disclosure provides an energy storage device comprising at least one electrochemical cell comprising a negative current collector, a negative electrode in electrical communication with the negative current collector, an electrolyte in electrical communication with the negative electrode, a positive electrode in electrical communication with the electrolyte and a positive current collector in electrical communication with the positive electrode. The negative electrode comprises an alkali metal. Upon discharge, the electrolyte provides charged species of the alkali metal. The positive electrode can include a Group IIIA, IVA, VA and VIA of the periodic table of the elements, or a transition metal (e.g., Group 12 element).
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: January 31, 2017
    Assignee: Ambri Inc.
    Inventors: David J. Bradwell, Xingwen Yu, Greg A. Thompson, Jianyi Cui, Alex Elliott, Chia-Ying Lee
  • Nano Wire Structure and Method for Fabricating the Same
    Publication number: 20160343620
    Abstract: A method comprises applying a first patterning process to a first photoresist layer to form a first opening, a second opening, a third opening and a fourth opening in the sacrificial layer, applying a second patterning process to a second photoresist layer to form a fifth opening, a sixth opening, a seventh opening and an eighth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the first and second patterning processes are substantially equal to each other, applying a third patterning process to a third photoresist layer to form a ninth opening, a tenth opening, an eleventh opening and a twelfth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the second and third patterning processes are substantially equal to each other and forming a plurality of nanowires based on the openings.
    Type: Application
    Filed: August 5, 2016
    Publication date: November 24, 2016
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Spacer etching process for integrated circuit design
    Patent number: 9502261
    Abstract: A method includes forming a first material layer on a substrate and performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer. The method further includes performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, wherein the second layout a cut pattern for the first layout. The method further includes forming spacer features on sidewalls of both the first and second pluralities of trenches, wherein the spacer features have a thickness and the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features. The method further includes removing the first material layer; forming a second material layer on the substrate and within openings defined by the spacer features; and removing the spacer features.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh, Ken-Hsien Hsieh, Ming-Feng Shieh, Shau-Lin Shue, Shih-Ming Chang, Tien-I Bao, Tsai-Sheng Gau
  • Method of semiconductor integrated circuit fabrication
    Patent number: 9496180
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) and the corresponding device are disclosed. A high-k/metal gate (HK/MG) and a conductive feature are disposed over a substrate, separated by a first dielectric layer. A global hard mask (GHM) layer is formed over the HK/MG, the conductive feature and the first dielectric layer. A second dielectric layer is then formed over the GHM layer. The second dielectric layer is etched to form a first opening to expose a portion of the HK/MG and a second opening to expose a portion of the conductive feature, by using the GHM layer as an etch stop layer. The GHM layer in the first opening and the second opening is then removed.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: November 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuen-Ming Liou, Chia-Ying Lee
  • REVERSE TONE SELF-ALIGNED CONTACT
    Publication number: 20160329406
    Abstract: The present disclosure relate to a method to an integrated chip having a source/drain self-aligned contact to a transistor or other semiconductor device. In some embodiments, the integrated chip has a pair of gate structures including a gate electrode arranged over a substrate and an insulating material arranged over the gate electrode. A source/drain region is arranged within the substrate between the pair of gate structures. An etch stop layer is arranged along sidewalls of the pair of gate structures and over the source/drain region, and a dielectric layer is over the insulating material. A source/drain contact is arranged over the insulating material and the etch stop layer and is separated from the sidewalls of the pair of gate structures by the etch stop layer. The source/drain contact is electrically coupled to the source/drain region.
    Type: Application
    Filed: July 21, 2016
    Publication date: November 10, 2016
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chia-Ying Lee
  • CUT FIRST SELF-ALIGNED LITHO-ETCH PATTERNING
    Publication number: 20160314972
    Abstract: The present disclosure relates to a method for performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a first cut layer over a hard mask having a first layer and an underlying second layer. A first plurality of openings are formed within the first layer and expose the second layer at a first plurality of positions. Two or more of the first plurality of openings are separated by the first cut layer. A spacer material is selectively formed onto sidewalls of the first plurality of openings within the first layer. A second plurality of openings are then formed within the first layer. The second plurality of openings are separated by a second cut layer including the spacer material and expose the second layer at a second plurality of positions. The second layer is etched according to the first layer and the spacer material.
    Type: Application
    Filed: July 6, 2016
    Publication date: October 27, 2016
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • CUT LAST SELF-ALIGNED LITHO-ETCH PATTERNING
    Publication number: 20160276154
    Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. In some embodiments, the method is performed by forming a spacer material within openings in a first masking layer overlying a second masking layer, and forming a reverse material over a part of the spacer material. A first plurality of openings are formed within the spacer material. The first plurality of openings are separated by the reverse material. A second plurality of openings are formed within the first masking layer. The second plurality of openings are separated by the spacer material. The second masking layer is patterned according to the first plurality of openings and the second plurality of openings.
    Type: Application
    Filed: June 1, 2016
    Publication date: September 22, 2016
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • High performance self aligned contacts and method of forming same
    Patent number: 9437712
    Abstract: A method embodiment includes forming a protective liner over the substrate and forming an inter-layer dielectric over the protective liner. The protective liner covers a sidewall of a gate spacer. The method further includes patterning a contact opening in the first ILD to expose a portion of the protective liner. The portion of the protective liner in the contact opening is removed to expose an active region at a top surface of the semiconductor substrate. A contact is formed in the contact opening. The contact is electrically connected to the active region.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Tai-Chun Huang, Chia-Ying Lee, Tze-Liang Lee
  • Cut first self-aligned litho-etch patterning
    Patent number: 9425049
    Abstract: The present disclosure relates to a method for performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a first cut layer over a substrate having a multi-layer hard mask with a first layer and an underlying second layer. A first plurality of openings, cut according to the first cut layer, are formed to expose the second layer at a first plurality of positions corresponding to a first plurality of shapes of a SALE design layer. A spacer material is deposited onto sidewalls of the multi-layer hard mask to form a second cut layer. A second plurality of openings, cut according to the second cut layer, are formed to expose the second layer at a second plurality of positions corresponding to a second plurality of shapes of the SALE design layer. The second layer is etched according to the first and second plurality of openings.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang