Patents by Inventor Chieh Hsieh

Chieh Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
    Publication number: 20230060720
    Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
  • METHOD AND APPARATUS FOR MITIGATING CONTAMINATION
    Publication number: 20230062653
    Abstract: Supersonic gas jets are provided near the immediate focus of a lithography apparatus in order to deflect tin debris generated by the lithography process away from a scanner side and towards a debris collection device. The gas jets can be positioned in a variety of useful orientations, with adjustable gas flow velocity and gas density in order to prevent up to nearly 100% of the tin debris from migrating to the reticle on the scanner side.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Chih-Ping YEN, Yen-Shuo SU, Chieh HSIEH, Shang-Chieh CHIEN, Chun-Lin CHANG, Li-Jui CHEN, Heng-Hsin LIU
  • PACKAGE HAVING PRISM STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230066363
    Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Hsiang Hsu, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Chung-Ming Weng
  • PROCESSOR CIRCUIT AND NON-TRANSITORY COMPUTER READABLE MEDIUM
    Publication number: 20230060855
    Abstract: A processor circuit includes a processor, N detection circuits and a neural network circuit. The processor is configured to provide a control signal. The control signal indicates an operational status of the processor. The N detection circuits are configured to detect N different types of variation factors affecting an operating voltage of the processor respectively, and accordingly generate N detection results respectively. N is an integer greater than one. The neural network circuit, coupled to the processor and the N detection circuits, is configured to determine the operating voltage of the processor according to the control signal and the N detection results.
    Type: Application
    Filed: June 15, 2022
    Publication date: March 2, 2023
    Inventor: HAN-CHIEH HSIEH
  • SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230065941
    Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, an insulating encapsulation, and a plurality of conductive pillars. The second semiconductor die is located on and electrically communicates to the first semiconductor die through joints therebetween. The insulating encapsulation encapsulates the first semiconductor die and the second semiconductor die and covers the joints. The plurality of conductive pillars is next to and electrically connected to the first semiconductor die and the second semiconductor die, and is covered by the insulating encapsulation.
    Type: Application
    Filed: August 29, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Tzuan-Horng Liu, Cheng-Chieh Hsieh, Tsung-Yuan Yu
  • Probe card device and self-aligned probe
    Patent number: 11592466
    Abstract: A probe card device and a self-aligned probe are provided. The self-aligned probe includes a fixing end portion configured to be abutted against a space transformer, a testing end portion configured to detachably abut against a device under test (DUT), a first connection portion connected to the fixing end portion, a second connection portion connected to the testing end portion, and an arced portion that connects the first connection portion and the second connection portion. The fixing end portion and the testing end portion jointly define a reference line passing there-through. The first connection portion has an aligned protrusion, and a maximum distance between the arced portion and the reference line is greater than 75 ?m and is less than 150 ?m.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: February 28, 2023
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Kai-Chieh Hsieh, Wei-Jhih Su, Hong-Ming Chen, Vel Sankar Ramachandran
  • Semiconductor package for thermal dissipation
    Patent number: 11594520
    Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Cheng-Chieh Hsieh, Ming-Yen Chiu
  • Semiconductor device and method of making the same
    Patent number: 11587883
    Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Chieh Hsieh, Hau Tao, Yung-Tien Kuo
  • Adaptive voltage scaling scanning method and associated electronic device
    Patent number: 11579643
    Abstract: The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: February 14, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chao-Min Lai, Hung-Wei Wang, Tang-Hung Chang, Han-Chieh Hsieh, Chun-Yi Kuo
  • CURRENT LOAD CIRCUIT AND CHIP FOR TESTING POWER SUPPLY CIRCUIT
    Publication number: 20230037496
    Abstract: A current load circuit for testing a power supply circuit includes a control circuit and a load generation circuit. The control circuit is configured to generate a reset signal according to a clock signal. The load generation circuit is coupled to the control circuit and has several load configurations. The load generation circuit is configured to provide one of the load configurations as a current load of the load generation circuit according to the clock signal and the reset signal and receive a portion of the supply current provided by the power supply circuit according to the current load to generate an indication signal for indicating a performance of the power supply circuit.
    Type: Application
    Filed: June 15, 2022
    Publication date: February 9, 2023
    Inventor: HAN-CHIEH HSIEH
  • FORMATION OF A BEAM WITH A FLAT-TOP PROFILE AND ELONGATED CROSS-SECTION AND USE OF SAME
    Publication number: 20230030757
    Abstract: Methodology of forming a substantially flat-top illuminating light beam, from a beam at the laser output having a conventionally non-uniform distribution of irradiance, with the use of only a birefringent prismatic element and light-focusing optics. Preferably, the cross-sectional area of such illuminating light distribution is shaped to be elongated or even substantially rectangular to have it used advantageously in various metrological situations such as, for example, the operation of a moving particle analyzer.
    Type: Application
    Filed: July 19, 2022
    Publication date: February 2, 2023
    Inventors: Yung-Chieh Hsieh, Chiayu Ai
  • EXTREME ULTRAVIOLET CONTROL SYSTEM
    Publication number: 20230030134
    Abstract: A method of controlling a droplet illumination module/droplet detection module system of an extreme ultraviolet (EUV) radiation source includes irradiating a target droplet with light from a droplet illumination module and detecting light reflected and/or scattered by the target droplet. The method includes determining whether an intensity of the detected light is within an acceptable range. In response to determining that the intensity of the detected light is not within the acceptable range, a parameter of the droplet illumination module is automatically adjusted to set the intensity of the detected light within the acceptable range.
    Type: Application
    Filed: October 10, 2022
    Publication date: February 2, 2023
    Inventors: Jen-Yang CHUNG, Chieh HSIEH, Shang-Chieh CHIEN, Li-Jui CHEN, Po-Chung CHENG
  • Board-like connector, dual-ring bridge of board-like connector, and wafer testing assembly
    Patent number: 11561244
    Abstract: A board-like connector, a dual-ring bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-ring bridges spaced apart from each other and an insulating layer. Each of the dual-ring bridges includes two carrying rings, two cantilevers respectively extending from and being coplanar with the two carrying rings, two abutting columns respectively extending from the two cantilevers along two opposite directions, and a bridging segment that connects the two carrying rings. The insulating layer connects the two carrying rings of the dual-ring bridges, and the two abutting columns of the dual-ring bridges respectively protrude from two opposite sides of the insulating layer. The two abutting columns of each of the dual-ring bridges are configured to be respectively abutted against two boards.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: January 24, 2023
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Kai-Chieh Hsieh, Chao-Chiang Liu, Meng-Chieh Cheng, Wei-Jhih Su
  • SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230018511
    Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
  • PROCESSOR WITH ADJUSTABLE OPERATING FREQUENCY
    Publication number: 20220416789
    Abstract: The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.
    Type: Application
    Filed: March 15, 2022
    Publication date: December 29, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Chao-Min Lai, Han-Chieh Hsieh, Tang-Hung Chang, Hung-Wei Wang, Chun-Yi Kuo
  • SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION
    Publication number: 20220413399
    Abstract: A coating is included on one or more components of a lithography system. The coating reduces surface roughness of the one or more surfaces, increases flatness of the one or more surfaces, and/or increases uniformity of the one or more surfaces. The coating may be formed on the one or more surfaces using one or more of the techniques described herein. The coating is configured to reduce adhesion of target material particles to the one or more surfaces, is configured to resist buildup of target material particles on the one or more surfaces, is configured to provide resistance against oxidation of the one or more surfaces, is configured to resist thermal damage of the one or more surfaces, and/or is configured to enable the lithography system to operate at higher operating temperatures, among other examples.
    Type: Application
    Filed: April 14, 2022
    Publication date: December 29, 2022
    Inventors: Shih-Yu TU, Chieh HSIEH, Shang-Chieh CHIEN, Sheng-Kang YU, Li-Jui CHEN, Heng-Hsin LIU
  • Probe card device and dual-arm probe
    Patent number: 11536744
    Abstract: A probe card device and a dual-arm probe are provided. The dual-arm probe has a probe length, and includes a bifurcation end portion and a testing end portion. The dual-arm probe has two broad side surfaces respectively arranged on two opposite sides thereof. The dual-arm probe has a separation slot that is recessed from a bifurcation opening of the bifurcation end portion toward the testing end portion and that penetrates from one of the two broad side surfaces to the other one, so that two branch arms of the dual-arm probe are defined by the separation slot and are spaced apart from each other. The separation slot has a slot length being 50% to 90% of the probe length. In a cross section of the two branch arms, an area of any one of the two branch arms is 90% to 110% of that of the other one.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: December 27, 2022
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Kai-Chieh Hsieh, Wei-Jhih Su, Hong-Ming Chen, Vel Sankar Ramachandran
  • EUV lithography system and method for decreasing debris in EUV lithography system
    Patent number: 11531278
    Abstract: Extreme ultraviolet (EUV) lithography systems are provided. A EUV scanner is configured to perform a lithography exposure process in response to EUV radiation. A light source is configured to provide the EUV radiation to the EUV scanner. A measuring device is configured to measure concentration of debris caused by unstable target droplets in the chamber. A controller is configured to adjust a first gas flow rate and a second gas flow rate in response to the measured concentration of the debris and a control signal from the EUV scanner. A exhaust device is configured to extract the debris out of the chamber according to the first gas flow rate. A gas supply device is configured to provide a gas into the chamber according to the second gas flow rate. The control signal indicates the lithography exposure process is completed.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi Yang, Ssu-Yu Chen, Shang-Chieh Chien, Chieh Hsieh, Tzung-Chi Fu, Bo-Tsun Liu, Li-Jui Chen, Po-Chung Cheng
  • Package structure and method of forming the same
    Patent number: 11532596
    Abstract: A package structure and method of forming the same are provided. The package structure includes a semiconductor unit, a package component and an underfill layer. The semiconductor structure unit includes a first semiconductor structure and a second semiconductor structure disposed as side by side, and an isolation region laterally between the first semiconductor structure and the second semiconductor structure. The isolation region vertically extends from a top surface to a bottom surface of the semiconductor structure unit. The semiconductor structure unit is disposed on and electrically connected to the package component. The underfill layer is disposed to fill a space between the semiconductor structure unit and the package component.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Contact pad for semiconductor device
    Patent number: 11527502
    Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Chia Huang, Tsung-Shu Lin, Cheng-Chieh Hsieh, Wei-Cheng Wu