Patents by Inventor Chien-Chang Huang

Chien-Chang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7091545
    Abstract: A memory device and fabricating method thereof. In the memory device of the present invention, a substrate has a plurality of deep trenches, wherein the deep trenches formed in the adjacent rows are staggered. A deep trench capacitor and a control gate are disposed in each deep trench successively. Word lines are disposed on the control gates respectively, and each word line is electrically coupled to the control gate thereunder. Diffusion regions are disposed in the substrate and surrounding the deep trenches respectively to serve as sources of vertical transistors. Each diffusion region is electrically connected to the surrounding deep trench capacitor. Active areas are disposed on the rows of the control gates respectively along a second direction. The regions where each active area overlaps the control gates have at least one indentation.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: August 15, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Tieh Chiang Wu, Chien-Chang Huang, Chin-Ling Huang, Bo Ching Jiang, Yu-Wei Ting
  • Publication number: 20060128041
    Abstract: A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.
    Type: Application
    Filed: January 26, 2006
    Publication date: June 15, 2006
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chien-Chang Huang, Tie-Jiang Wu, Chin-Ling Huang, Yu-Wei Ting, Bo-Ching Jiang
  • Patent number: 7053932
    Abstract: A method to detect the movement of an image sensor. Movement is detected according to a first, second, third, and fourth frame, all captured by the image sensor. A first captured image region is captured from the first frame. Then, a first corresponding region matching the first captured image region is captured from the second frame, wherein the first corresponding region shifts in a predetermined direction relative to the first captured image region. Next, a second captured image region is captured from the third frame, wherein the second captured image region shifts in a direction opposite to the predetermined direction relative to the first captured image region. Then, a second corresponding region matching the second captured image region is captured from the fourth frame. Finally, the movement of the image sensor is determined according to the second captured image region and the second corresponding region.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: May 30, 2006
    Assignee: PixArt Imaging Inc.
    Inventors: Chun-Huang Lin, Jeng-Feng Lan, Chien-Chang Huang
  • Publication number: 20060108507
    Abstract: An active pixel sensor includes a photosensitive element, and first and second transistors. The photosensitive element generates an electrical signal in response to detected light, and updates the electrical signal in response to a reset signal. The first transistor is coupled electrically to the photosensitive element, and amplifies the electrical signal to result in an output signal. The second transistor is coupled electrically to the first transistor, and is responsive to a row select signal for controlling output of the output signal. An image sensing module built from active pixel sensors is also disclosed.
    Type: Application
    Filed: March 4, 2005
    Publication date: May 25, 2006
    Applicant: Pixart Imaging Inc.
    Inventor: Chien-Chang Huang
  • Patent number: 7050043
    Abstract: An optical apparatus. The optical apparatus is applied to an object surface, comprising a frame, a light emitting device and an optical sensor. The frame is disposed in the optical apparatus, having a first compartment and a second compartment, wherein the first compartment has a first opening and the second compartment has a second opening. The light emitting device is disposed in the first compartment, wherein light emitted from the light emitting device passes through the first opening and is reflected by the object surface outside the frame. The optical sensor is disposed in the second compartment to receive light reflected from the object surface passing through the second opening.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: May 23, 2006
    Assignee: PixArt Imagning Inc.
    Inventors: Chien-Chang Huang, Chun-Huang Lin, Jeng-Feng Lan
  • Publication number: 20060094178
    Abstract: A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.
    Type: Application
    Filed: July 5, 2005
    Publication date: May 4, 2006
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Shian-Jyh Lin, Sheng-Tsung Chen, Neng-Tai Shih, Chien-Chang Huang, Chien-Jung Yang, Yi-Jung Chen
  • Patent number: 7026647
    Abstract: A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: April 11, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Tie Jiang Wu, Chien-Chang Huang, Bo Ching Jiang, Yu-Wei Ting, Chin-Ling Huang
  • Patent number: 7015050
    Abstract: A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: March 21, 2006
    Assignee: Nanya Techonolgy Corporation
    Inventors: Chien-Chang Huang, Tie-Jiang Wu, Chin-Ling Huang, Yu-Wei Ting, Bo-Ching Jiang
  • Patent number: 6984534
    Abstract: Method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, and a test device thereof. In the present invention a plurality of memory cells are formed in the memory area and at least one test device is formed in the scribe line region simultaneously. A first resistance and a second resistance are detected by the test device. Normal alignment of the bit line and the bar-type active area of the test device is determined according to the first resistance and the second resistance. Finally, whether the alignment of the bit line contacts and the active areas in memory areas is normal is determined according to whether the alignment of the bit line contact and bar-type active area of the test device is normal.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: January 10, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Tie Jiang Wu, Chien-Chang Huang, Yu-Wei Ting, Bo Ching Jiang, Chin-Ling Huang
  • Patent number: 6959821
    Abstract: A display detecting apparatus for detecting display modules having a display surface, includes a base, at least one flat panel generally horizontally fixed on the base; and a plurality of frames fixed on the flat panel for carrying the display modules, wherein at least two adjacent frames form a first angle less than 180 degrees.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: November 1, 2005
    Assignee: Hannstar Display Corp.
    Inventor: Chien Chang Huang
  • Publication number: 20050230597
    Abstract: An image sensing device includes a plurality of color units. Each color unit has a photosensor element for converting light of a specific spectrum range into an electrical signal. Different arrangements of the photosensor elements are set in diagonal directions. In this way, such layout is capable of reducing color shift effect.
    Type: Application
    Filed: November 24, 2004
    Publication date: October 20, 2005
    Inventors: Chih-Cheng Hsieh, Chien-Chang Huang
  • Patent number: 6946678
    Abstract: A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: September 20, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Tie Jiang Wu, Chien-Chang Huang, Yu-Wei Ting, Bo Ching Jiang
  • Publication number: 20050202579
    Abstract: A method of forming a solid-state image sensor is provided. The method includes the steps of forming a plurality of photosensor elements on a substrate; forming a plurality of color filters on the plurality of photosensors; forming a light blocking member between adjacent color filters; and forming a plurality of microlenses on the plurality of color filters. Each photosensor with each corresponding color filter and microlens is used for receiving an incident light of specific spectrum.
    Type: Application
    Filed: September 30, 2004
    Publication date: September 15, 2005
    Inventors: Chien-Chang Huang, Chih-Cheng Hsieh
  • Publication number: 20050184289
    Abstract: A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.
    Type: Application
    Filed: March 30, 2005
    Publication date: August 25, 2005
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Tie Wu, Chien-Chang Huang, Bo Jiang, Yu-Wei Ting, Chin-Ling Huang
  • Publication number: 20050139944
    Abstract: An optical navigation chip. The optical navigation chip is appropriate for an optical pointing device and used for calculating a displacement of the optical navigation chip relative to an operating surface. The optical navigation chip comprises a photo sensor array driven by a photo sensor control circuit for detecting an image of the operating surface, a signal readout circuit coupled with the photo sensor array for reading out the image in analog format, an analog-to-digital conversion (ADC) circuit coupled with the signal readout circuit for converting the image from analog format to digital format, an image qualification circuit coupled with the ADC circuit for determining quality of the image and outputting a quality index accordingly, and a motion detection circuit for outputting the displacement according to the quality index.
    Type: Application
    Filed: June 2, 2004
    Publication date: June 30, 2005
    Inventors: Chun-Huang Lin, Jeng-Feng Lan, Chien-Chang Huang
  • Patent number: 6902942
    Abstract: A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices with vertical transistors. In the test device, an active area is disposed in the scribe line region. An H-type deep trench capacitor is disposed in the active area, and has parallel first and second portions and a third portion. Each of the first and second portions has a center and two ends. The third portion is disposed between the centers of the first and second portions. First to fourth conductive pads are disposed on the two ends of the first and second portions respectively. A bar-type conductive pad is disposed between the first and second portions, having a center aligned with a center of the third portion.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: June 7, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Tie Jiang Wu, Chien-Chang Huang, Bo Ching Jiang, Yu-Wei Ting, Chin-Ling Huang
  • Publication number: 20050104109
    Abstract: A memory device and fabricating method thereof. In the memory device of the present invention, a substrate has a plurality of deep trenches, wherein the deep trenches formed in the adjacent rows are staggered. A deep trench capacitor and a control gate are disposed in each deep trench successively. Word lines are disposed on the control gates respectively, and each word line is electrically coupled to the control gate thereunder. Diffusion regions are disposed in the substrate and surrounding the deep trenches respectively to serve as sources of vertical transistors. Each diffusion region is electrically connected to the surrounding deep trench capacitor. Active areas are disposed on the rows of the control gates respectively along a second direction. The regions where each active area overlaps the control gates have at least one indentation.
    Type: Application
    Filed: December 20, 2004
    Publication date: May 19, 2005
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Tieh Wu, Chien-Chang Huang, Chin-Ling Huang, Bo Ching Jiang, Yu-Wei Ting
  • Patent number: 6891216
    Abstract: A test structure of a DRAM array includes a substrate. A transistor is formed on the substrate and has a first region and a second region as source/drain regions thereof. A deep trench capacitor is formed adjacent to the transistor and has a first width. A shallow trench isolation is formed in a top portion of the deep trench capacitor and has a second width. The second width is substantially shorter than the first one. A third region is formed adjacent to the deep trench capacitor. A first contact is formed on the substrate and contacts with the first region. A second contact is formed on the substrate and contacts with the third region.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: May 10, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Chien-Chang Huang, Tie-Jiang Wu, Chin-Ling Huang, Yu-Wei Ting, Bo-Ching Jiang
  • Patent number: 6875654
    Abstract: A memory device and fabricating method thereof. In the memory device of the present invention, a substrate has a plurality of deep trenches, wherein the deep trenches formed in the adjacent rows are staggered. A deep trench capacitor and a control gate are disposed in each deep trench successively. Word lines are disposed on the control gates respectively, and each word line is electrically coupled to the control gate thereunder. Diffusion regions are disposed in the substrate and surrounding the deep trenches respectively to serve as sources of vertical transistors. Each diffusion region is electrically connected to the surrounding deep trench capacitor. Active areas are disposed on the rows of the control gates respectively along a second direction. The regions where each active area overlaps the control gates have at least one indentation.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: April 5, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Tieh Chiang Wu, Chien-Chang Huang, Chin-Ling Huang, Bo Ching Jiang, Yu-Wei Ting
  • Patent number: 6844207
    Abstract: Method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, and a test device thereof. In the present invention a plurality of memory cells are formed in the memory area and at least one test device is formed in the scribe line region simultaneously. A first resistance and a second resistance are detected by the test device. Normal alignment of the bit line and the bar-type active area of the test device is determined according to the first resistance and the second resistance. Finally, whether the alignment of the bit line contacts and the active areas in memory areas is normal is determined according to whether the alignment of the bit line contact and bar-type active area of the test device is normal.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: January 18, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Tie Jiang Wu, Chien-Chang Huang, Yu-Wei Ting, Bo Ching Jiang, Chin-Ling Huang