Patents by Inventor Chien-Hung Liu

Chien-Hung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip package and fabrication method thereof
    Patent number: 8922026
    Abstract: The invention provides A chip package, comprising: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region, and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; and a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures, wherein the heavily doped regions are disposed in a carrier substrate which is bonded to the first surface of the semiconductor substrate.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: December 30, 2014
    Inventors: Chien-Hung Liu, Cheng-Te Chou
  • COMPUTER SYSTEM AND ITS POWER ADAPTER WITH IMAGE PROJECTION FUNCTION
    Publication number: 20140359314
    Abstract: A computer system and its power adapter with image projection function are provided. The computer system includes an electronic device and a power adapter. The power adapter includes a waveform-transforming module and an image-projecting module electrically connected to the waveform-transforming module. When the power adapter electrically connects to both a power source and the electronic device, the waveform-transforming module provides power to the electronic device and the image-projecting module, and the electronic device provides image signals to the image-projecting module.
    Type: Application
    Filed: November 1, 2013
    Publication date: December 4, 2014
    Applicant: Quanta Computer Inc.
    Inventors: Sheng-Tzu SU, Chien-Hung LIU, Pei-Te LIU
  • IMAGE SENSOR PACKAGE WITH TRENCH INSULATOR AND FABRICATION METHOD THEREOF
    Publication number: 20140319670
    Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Inventors: Wen-Cheng CHIEN, Wen-Ken HUANG, Chien-Hung LIU, Joey LAI
  • Chip package
    Patent number: 8872196
    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a sensor region formed in the semiconductor substrate; a light emitting device disposed on the second surface of the semiconductor substrate; at least one first conducting bump disposed on the first surface of the semiconductor substrate and electrically connected to the sensor region; at least one second conducting bump disposed on the first surface of the semiconductor substrate and electrically connected to the light emitting device; and an insulating layer located on the semiconductor substrate to electrically insulate the semiconductor substrate from the at least one first conducting bump and the at least one second conducting bump.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: October 28, 2014
    Inventors: Po-Han Lee, Chien-Hung Liu
  • Method for detecting and removing scrolling texts during video communication
    Patent number: 8867832
    Abstract: A method for detecting and removing scrolling texts comprising a step of using an adaptive transient difference processing of video communication to conduct frame calculation, wherein the adaptive transient difference processing takes first N frames fjkt?N and a current frame fjkt, and subtracts them to obtain a frame difference; and if the frame difference is greater than a threshold value, it is determined that the current frame fjkt has scrolling texts; and interpolates the first N frames before the current position of the scrolling texts to replace the current frame fjkt to achieve the goal of hiding the scrolling texts during video communication to enhance the viewing effect.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: October 21, 2014
    Assignee: National Yunlin University of Science and Technology
    Inventors: Shih-Chang Hsia, Chien-Hung Liu
  • UNIVERSAL SERIAL BUS TESTING DEVICE
    Publication number: 20140304555
    Abstract: A USB testing device is provided for an electronic device having a USB port. The USB testing device includes a first USB control unit, a second USB control unit, and a micro-processor. When the first USB control unit has received power, the first USB control unit processes a connection test via a first data port. When the second USB control unit has received the power, the second USB control unit processes a connection test via a second data port. When the USB testing device is connected to the USB port, the micro-processor provides power to the first USB control unit. When the first USB control unit receives power, the first USB control unit provides power to the second USB control unit after waiting for a predetermined period of time. The electronic device determines whether the first and second data ports are operating properly.
    Type: Application
    Filed: September 11, 2013
    Publication date: October 9, 2014
    Applicant: Quanta Computer Inc.
    Inventor: Chien-Hung Liu
  • SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD AND OPERATING METHOD OF THE SAME
    Publication number: 20140264545
    Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.
    Type: Application
    Filed: May 10, 2013
    Publication date: September 18, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Hung Wang, Jyun-Siang Huang, Chien-Hung Liu, Chia-Wen Cheng, Ying-Tso Chen
  • Electronic device package and method for fabricating the same
    Patent number: 8823179
    Abstract: An embodiment of the present invention provides an electronic device package, which includes a chip having a first surface and an opposite second surface and a trench extending into a body of the chip along a direction from the second surface to the first surface, wherein a bottom portion of the trench includes at least two contact holes.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: September 2, 2014
    Inventors: Chia-Lun Tsai, Wen-Cheng Chien, Po-Han Lee, Wei-Ming Chen, Chien-Hung Liu, Ying-Nan Wen
  • Bit line structure, semiconductor device and method of forming the same
    Patent number: 8809933
    Abstract: A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: August 19, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Guan-De Lee, Chien-Hung Liu, Shou-Wei Huang, Ying-Tso Chen
  • CHIP SCALE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20140225237
    Abstract: A chip scale package structure includes a chip, a dam unit, a board body, a plurality of first conductors, an encapsulating glue, a plurality of first conductive layers, an isolation layer, and a plurality of first electrodes. The dam unit is disposed on the surface of the chip. The board body is located on the dam unit. The first conductors are respectively in electrical contact with the conductive pads of the chip. The encapsulating glue covers the surface of the chip, and the board body and the first conductors are packaged in the encapsulating glue. The first conductive layers are located on the surface of the encapsulating glue opposite to the chip and respectively in electrical contact with the first conductors. The isolation layer is located on the encapsulating glue and the first conductive layers. The first electrodes are respectively in electrical contact with the first conductive layers.
    Type: Application
    Filed: February 4, 2014
    Publication date: August 14, 2014
    Applicant: XINTEC INC.
    Inventors: Chien-Hung LIU, Ying-Nan WEN
  • METHOD FOR DETECTING AND REMOVING SCROLLING TEXTS DURING VIDEO COMMUNICATION
    Publication number: 20140219555
    Abstract: A method for detecting and removing scrolling texts comprising a step of using an adaptive transient difference processing of video communication to conduct frame calculation, wherein the adaptive transient difference processing takes first N frames fjkt?N and a current frame fjkt, and subtracts them to obtain a frame difference; and if the frame difference is greater than a threshold value, it is determined that the current frame fjkt has scrolling texts; and interpolates the first N frames before the current position of the scrolling texts to replace the current frame fjkt to achieve the goal of hiding the scrolling texts during video communication to enhance the viewing effect.
    Type: Application
    Filed: February 1, 2013
    Publication date: August 7, 2014
    Applicant: National Yunlin University of Science and Technology
    Inventors: Shih-Chang Hsia, Chien-Hung Liu
  • Capacitive coupler packaging structure
    Patent number: 8791768
    Abstract: Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, wherein the at least one capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, and the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: July 29, 2014
    Inventors: Ho-Yin Yiu, Chien-Hung Liu, Ying-Nan Wen, Shih-Yi Lee, Wei-Chung Yang, Bai-Yao Lou, Hung-Jen Lee
  • Electronic device and protection mechanism thereof
    Patent number: 8789754
    Abstract: An electronic device includes a protection mechanism, a first circuit board having a first electronic loop, and a second circuit board having a second electronic loop. The protection mechanism is disposed between the first circuit board and the second circuit board, and includes a frame and a first flexible board. The first flexible board includes a first connector, and a first wire mesh used for forming a third electronic loop. When trace breaking occurs to any one, any two, or all of the electronic loops, the first, the second, and the third electronic loops are forced to break, thereby protecting data saved in the electronic device from being read inappropriately, so as to avoid data to be stolen.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: July 29, 2014
    Assignee: Uniform Industrial Corp.
    Inventors: Yi-Yuan Chiu, Yu-Tsung Chen, Shu-Hua Chiang, Chien-Hung Liu
  • Electronic device package and fabrication method thereof
    Patent number: 8778798
    Abstract: An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: July 15, 2014
    Inventors: Shu-Ming Chang, Bai-Yao Lou, Ying-Nan Wen, Chien-Hung Liu
  • ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF
    Publication number: 20140193950
    Abstract: An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.
    Type: Application
    Filed: March 12, 2014
    Publication date: July 10, 2014
    Applicant: XINTEC INC.
    Inventors: Shu-Ming CHANG, Bai-Yao LOU, Ying-Nan WEN, Chien-Hung LIU
  • Image sensor package with trench insulator and fabrication method thereof
    Patent number: 8772919
    Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: July 8, 2014
    Inventors: Wen-Cheng Chien, Wen-Ken Huang, Chien-Hung Liu, Joey Lai
  • Chip package with heavily doped region and fabrication method thereof
    Patent number: 8748949
    Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: June 10, 2014
    Inventors: Chien-Hung Liu, Cheng-Te Chou
  • Chip package and fabrication method thereof
    Patent number: 8722463
    Abstract: The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 13, 2014
    Inventor: Chien-Hung Liu
  • Common repair structures for close bus in a liquid crystal display
    Patent number: 8724062
    Abstract: One aspect of the present disclosure relates to a common repair structure for repairing scanning and/or data line defects in a liquid crystal display panel. In one embodiment, the common repair structure includes a plurality of “H” shaped structures, where each “H” shaped structure is placed over a corresponding segment of two neighboring scanning lines located between and associated with two neighboring pixels along the second direction or a corresponding segment of two neighboring data lines located between and associated with two neighboring pixels along the first direction.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: May 13, 2014
    Assignee: Au Optronics Corporation
    Inventor: Chien-Hung Liu
  • Power supply system
    Patent number: 8723485
    Abstract: A power supply system includes an output node, an internal power supply unit, a boost storage unit, a charging path unit, and a discharging path unit. The output node is coupled to a load device. The internal power supply unit includes a gold capacitor unit for storing an internal storage voltage. The charging path unit is turned on in a charging period to store a boost supply voltage in the boost storage unit. The discharging path is turned on in a discharging period to provide a power signal for drive the load device according to the internal storage voltage and the boost supply voltage. The charging and discharging periods are non-overlapping.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: May 13, 2014
    Assignee: Quanta Computer Inc.
    Inventor: Chien-Hung Liu