Patents by Inventor Chien Liu

Chien Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fin field-effect transistor structure and manufacturing process thereof
    Patent number: 8664055
    Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: March 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • MOS TRANSISTOR AND PROCESS THEREOF
    Publication number: 20140042501
    Abstract: A MOS transistor includes a gate structure and a spacer. The gate structure is located on a substrate. The spacer is located on the substrate beside the gate structure, and the spacer includes an L-shaped inner spacer and an outer spacer, wherein the outer spacer is located on the L-shaped inner spacer, and the two ends of the L-shaped inner spacer protrude from the outer spacer. Moreover, the present invention also provides a MOS transistor process for forming the MOS transistor.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 13, 2014
    Inventors: Jei-Ming Chen, Chih-Chien Liu, Yu-Shu Lin, Tzu-Chin Wu
  • Method of forming semiconductor device
    Patent number: 8647941
    Abstract: A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Method of forming opening on semiconductor substrate
    Patent number: 8647989
    Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Po-Chun Chen
  • AIR RATCHET WRENCH
    Publication number: 20140020516
    Abstract: An air ratchet wrench includes a wrench body, a rotary driving head, an airflow unit formed in the wrench body, a switch unit, a driving unit and a valve assembly. The airflow unit includes a primary air path and a pair of head-directing paths. When the driving unit is triggered, airflow is permitted to enter the primary air path for driving rotation of the driving head, and is prevented from entering any of the head-directing paths. When the driving unit is not triggered, airflow is prevented from entering the primary air path, and is allowed by the valve assembly to enter one of the head-directing paths selected through user operation of the switch unit for controlling rotation direction of the driving head.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 23, 2014
    Inventors: Chien-An Liu, Chun-Chi Lai
  • SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    Publication number: 20130334650
    Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Jei-Ming Chen, Jui-Min Lee, Yuh-Min Lin
  • Print head pulsing techniques for multicolor printers
    Patent number: 8610750
    Abstract: In one aspect of the invention there is disclosed a multicolor thermal imaging system wherein different heating elements on a thermal print head can print on different color-forming layers of a multicolor thermal imaging member in a single pass. The line-printing time is divided into portions, each of which is divided into a plurality of subintervals. All of the pulses within the portions have the same energy. In one embodiment, every pulse has the same amplitude and duration. Different colors are selected for printing during the different portions by varying the fraction of subintervals that contain pulses. This technique allows multiple colors to be printed using a thermal print head with a single strobe signal line. Pulsing patterns may be chosen to reduce the coincidence of pulses provided to multiple print head elements, thereby reducing the peak power requirements of the print head.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: December 17, 2013
    Assignee: Zink Imaging, Inc.
    Inventors: Chien Liu, William T. Vetterling
  • Fabrication method and structure of through silicon via
    Patent number: 8609529
    Abstract: A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: December 17, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Fu Lin, Chun-Yuan Wu, Chih-Chien Liu, Teng-Chun Tsai, Chin-Cheng Chien
  • PRINT HEAD PULSING TECHNIQUES FOR MULTICOLOR PRINTERS
    Publication number: 20130286135
    Abstract: In one aspect of the invention there is disclosed a multicolor thermal imaging system wherein different heating elements on a thermal print head can print on different color-forming layers of a multicolor thermal imaging member in a single pass. The line-printing time is divided into portions, each of which is divided into a plurality of subintervals. All of the pulses within the portions have the same energy. In one embodiment, every pulse has the same amplitude and duration. Different colors are selected for printing during the different portions by varying the fraction of subintervals that contain pulses. This technique allows multiple colors to be printed using a thermal print head with a single strobe signal line. Pulsing patterns may be chosen to reduce the coincidence of pulses provided to multiple print head elements, thereby reducing the peak power requirements of the print head.
    Type: Application
    Filed: June 26, 2013
    Publication date: October 31, 2013
    Inventors: Chien Liu, William T. Vetterling
  • Non-Planar FET and Manufacturing Method Thereof
    Publication number: 20130270612
    Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.
    Type: Application
    Filed: April 16, 2012
    Publication date: October 17, 2013
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Chia-Lin Hsu
  • Optical disc with thermally-printable surface
    Patent number: 8557361
    Abstract: An optical disc is described that bears, on one surface, a plurality of color-forming layers that can form a multicolored image when heated in contact with a thermal print head. The color-forming composition comprises color-forming layers and thermally-insulating spacers and is designed such that warping of the optical disc in conditions of changing temperature and humidity is minimized. The compliance of the color-forming composition is such that intimate contact between the thermal print head and the printable surface of the disc can be maintained as one is translated relative to the other. Methods for assembling such an optical disc are provided.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: October 15, 2013
    Assignee: Zink Imaging, Inc.
    Inventors: Yulin Hardin, Stephen Robert Herchen, Dana Frederic Schuh, William T. Vetterling, Michael Armour Young, Stephen J. Telfer, Chien Liu
  • Method for manufacturing multi-gate transistor device
    Patent number: 8551829
    Abstract: A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: October 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • NON-PLANAR SEMICONDUCTOR STRUCTURE
    Publication number: 20130228836
    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. Anon-planar semiconductor process is also provided for forming the semiconductor structure.
    Type: Application
    Filed: April 24, 2013
    Publication date: September 5, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hung Tsai, Chien-Ting Lin, Chin-Cheng Chien, Chin-Fu Lin, Chih-Chien Liu, Teng-Chun Tsai, Chun-Yuan Wu
  • METHOD FOR FABRICATING FINFETS AND SEMICONDUCTOR STRUCTURE FABRICATED USING THE METHOD
    Publication number: 20130207122
    Abstract: A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chun-Yuan Wu, Teng-Chun Tsai, Chih-Chien Liu
  • Hard disk carrying apparatus
    Patent number: 8508930
    Abstract: The invention discloses a hard disk carrying apparatus comprising a main body, a plurality of slide racks, and a plurality of valves. In the main body, an accommodating space is concavely disposed at a front side of the main body; a plurality of primary slide rails that are adjacent and parallel to each other are disposed on a bottom wall in the accommodating space; a plurality of secondary slide rails is disposed on a top wall in the accommodating space. Each of the plurality of slide racks is a long rack. Each of the plurality of valves is a long door plate member. An end of each valve is a pivot end that is pivotally installed at a bottom edge of the front side of the main body; the other end of the valve is a latch end that includes a locking element disposed thereon.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: August 13, 2013
    Assignee: Promise Technology, Inc.
    Inventors: Cheng-Tzu Peng, Char T. Vijay, Hsiang-Chien Liu, Chuan-Yi Yeh, Chia-Wei Fan
  • Multicolor thermal imaging method and thermal printer
    Patent number: 8502848
    Abstract: A multicolor direct thermal imaging method wherein a multicolor image is formed in a thermal imaging member comprising at least first and second different image-forming compositions and a thermal printer for use in practicing the method. Heat is applied to at least the second image-forming composition while the first image-forming composition is at a first baseline temperature (T1) to form an image in at least the second image-forming composition, and heat is applied to at least the first image-forming composition while it is at a second baseline temperature (T2) to form an image in at least the first image-forming composition, wherein T1 is different from T2.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: August 6, 2013
    Assignee: Zink Imaging, Inc.
    Inventors: Brian D. Busch, Fariza B. Hasan, Chien Liu, Stephen J. Telfer, William T. Vetterling
  • Print head pulsing techniques for multicolor printers
    Patent number: 8502846
    Abstract: In one aspect of the invention there is disclosed a multicolor thermal imaging system wherein different heating elements on a thermal print head can print on different color-forming layers of a multicolor thermal imaging member in a single pass. The line-printing time is divided into portions, each of which is divided into a plurality of subintervals. All of the pulses within the portions have the same energy. In one embodiment, every pulse has the same amplitude and duration. Different colors are selected for printing during the different portions by varying the fraction of subintervals that contain pulses. This technique allows multiple colors to be printed using a thermal print head with a single strobe signal line. Pulsing patterns may be chosen to reduce the coincidence of pulses provided to multiple print head elements, thereby reducing the peak power requirements of the print head.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: August 6, 2013
    Assignee: Zink Imaging, Inc.
    Inventors: Chien Liu, William T. Vetterling
  • Fabrication method and structure of through silicon via
    Publication number: 20130193585
    Abstract: A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Inventors: Chin-Fu Lin, Chun-Yuan Wu, Chih-Chien Liu, Teng-Chun Tsai, Chin-Cheng Chien
  • Semiconductor process
    Patent number: 8497198
    Abstract: A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 30, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • HIGH ELECTRON MOBILITY GaN-BASED TRANSISTOR STRUCTURE
    Publication number: 20130175537
    Abstract: A high electron mobility GaN-based transistor structure comprises a substrate, an epitaxial GaN layer formed on the substrate, at least one ohmic contact layer formed on the epitaxial GaN layer, a metallic gate layer formed on the epitaxial GaN layer, and a diffusion barrier layer interposed between the metallic gate layer and the epitaxial GaN layer. The diffusion barrier layer hinders metallic atoms of the metallic gate layer from diffusing into the epitaxial GaN layer, whereby are improved the electric characteristics and reliability of the GaN-based transistor.
    Type: Application
    Filed: April 25, 2012
    Publication date: July 11, 2013
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: EDWARD YI CHANG, CHIA-HUA CHANG, YUEH-CHIN LIN, YU KONG CHEN, SHIH-CHIEN LIU