Patents by Inventor Chien Liu

Chien Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20150064896
    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu
  • METHOD AND IMPROVED PHARMACEUTICAL COMPOSITION FOR ENHANCING TRANSDERMAL DELIVERY OF PDE-5 INHIBITOR
    Publication number: 20150057284
    Abstract: The present disclosure relates to the use of an agent that enhances transdermal delivery of a PDE-5 inhibitor. More particularly, the present disclosure provides improved method and composition that promotes transdermal delivery of a PDE-5 inhibitor for the treatment of the PDE-5 mediated conditions and/or diseases.
    Type: Application
    Filed: December 26, 2011
    Publication date: February 26, 2015
    Applicant: Tritech Biopharmaceuticals Co., Ltd.
    Inventors: Yee-Chien Liu, Pei-Ling Wu
  • Method of forming opening on semiconductor substrate
    Patent number: 8962486
    Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Po-Chun Chen
  • SPATIAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME
    Publication number: 20150048486
    Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hung-Lin Shih, Chih-Chien Liu, Jei-Ming Chen, Wen-Yi Teng, Chieh-Wen Lo
  • Apparatuses and methods for providing multi-standby mode of wireless communications using single subscriber identity card with multiple subscriber numbers
    Patent number: 8954114
    Abstract: A communication device is provided with a processing unit. The processing unit determines whether at least one elementary file in a single subscriber identity card is required to be read out. If so, the processing unit activates one subscriber identity module instance in the subscriber identity card for the elementary file, and reads the elementary file from the subscriber identity card.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: February 10, 2015
    Assignee: MediaTek Inc
    Inventors: Chih-Hung Lee, Min-Ju Wu, Nai-Hsin Chang, Jen-Chien Liu
  • Method for forming a FinFET structure
    Patent number: 8951884
    Abstract: A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: February 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Jei-Ming Chen, Chih-Chien Liu, Chin-Fu Lin, Kuan-Hsien Li
  • Computer booting method and computer system
    Patent number: 8954805
    Abstract: A computer booting method is provided for a computer system. The method comprises performing a power-on-self test. When the test result shows no error on the BIOS, a booting procedure is executed. When the test result shows the BIOS is damaged, whether the computer system stores a backup file of the BIOS is determined. When the computer system stores the backup file, the central processing unit reads the data of backup file and write it into a BIOS system memory and a reboot process is performed. When there is no backup file in the computer system, the computer system is connected to an internet server and downloads a BIOS backup file to the system main memory from the internet server. The central processing unit reads the BIOS backup file and write it into the BIOS system memory and a reboot process is formed.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: February 10, 2015
    Assignee: Compal Electronics, Inc.
    Inventors: Chih-Chien Liu, Feng-Hsun Chen, Chia-Tsung Cheng
  • Transistor with non-uniform stress layer with stress concentrated regions
    Patent number: 8937369
    Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: January 20, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Yu-Shu Lin, Jei-Ming Chen, Wen-Yi Teng
  • Method of fabricating dielectric layer and shallow trench isolation
    Patent number: 8927388
    Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: January 6, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Jei-Ming Chen, Wen-Yi Teng, Chia-Lung Chang, Chih-Chien Liu
  • METAL GATE STRUCTURE AND FABRICATION METHOD THEREOF
    Publication number: 20150004780
    Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.
    Type: Application
    Filed: September 19, 2014
    Publication date: January 1, 2015
    Inventors: Tsun-Min Cheng, Min-Chuan Tsai, Chih-Chien Liu, Jen-Chieh Lin, Pei-Ying Li, Shao-Wei Wang, Mon-Sen Lin, Ching-Ling Lin
  • Semiconductor device
    Patent number: 8921944
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a metal-oxide semiconductor (MOS) transistor disposed in the substrate; and a shallow trench isolation (STI) disposed in the substrate and around the MOS transistor, in which the STI comprises a stress material.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Yuan Wu, Chih-Chien Liu
  • METHOD OF FABRICATING SEMICONDUCTOR PATTERNS
    Publication number: 20140370701
    Abstract: A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chin-Fu Lin, Chih-Chien Liu, Chia-Lin Hsu, Chin-Cheng Chien, Chun-Yuan Wu
  • SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    Publication number: 20140367779
    Abstract: A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a vacant part. The gate surrounds the vacant part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a vacant part in the corresponding top part, thereby forming the vacant part over a through hole. A gate is formed to surround the vacant part.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chia-Lin Hsu
  • SEMICONDUCTOR STRUCTURE WITH DIFFERENT FINS OF FINFETS
    Publication number: 20140332824
    Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.
    Type: Application
    Filed: July 24, 2014
    Publication date: November 13, 2014
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chun-Yuan Wu, Teng-Chun Tsai, Chih-Chien Liu
  • REAL-TIME VIDEO ANNOTATION LEARNING SYSTEM AND METHOD FOR THE SAME
    Publication number: 20140335502
    Abstract: A real-time video annotation learning system and a method for the same are revealed. The real-time video annotation learning system includes a video management module, an annotation management module and a data storage module. A language learner can select videos stored in the data storage module by the video management module and add comments to a location of an image in the video at a specific time while the comments are in the form of text or graphs built in a commentary management module. Thus the comments are shown on the image in the form of text or graphs at a specific time. Users can grasp key points of learning content the video provided exactly. Together with system functions of real-time word look-up and word note, user's learning effect is significantly improved and the video has an advantage in language learning.
    Type: Application
    Filed: September 13, 2013
    Publication date: November 13, 2014
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: YUEH-MIN HUANG, CHIA-JU LIU, HSIN-CHIN CHEN, MING-CHI LIU, TZU-CHIEN LIU, FU-YUN YU, YEN-HUNG KUO
  • METHOD AND SYSTEM FOR REMINDING READER OF FATIGUE IN READING WHILE USING ELECTRONIC DEVICE
    Publication number: 20140333435
    Abstract: The method and system for reminding readers of fatigue in reading while using electronic devices are revealed. First use a reading speed calculation module to detect user's reading speed within a period of time when the user is using an electronic with a display to read. The reading speed is related to pages being turned or the amount of words being read. Then a fatigue-in-reading reminder module is activated by the reading speed calculation module when the user's reading speed falls within a specific range so as to remind the user by pop-up windows, sounds, flash light or vibration at the proper time and provide the user certain corresponding measures he/she should take. Thereby there is no need to use additional equipment for preventing users from becoming more fatigue and healthy vision is accomplished at lower cost with higher efficiency.
    Type: Application
    Filed: July 19, 2013
    Publication date: November 13, 2014
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: YUEH-MIN HUANG, CHIA-JU LIU, CHIA-HUNG LAI, YEN-NING SU, CHIA-CHENG HSU, YU-CHENG CHIEN, TSUNG-HO LIANG, TZU-CHIEN LIU, FU-YUN YU, YU-LIN JENG
  • Metal gate structure and fabrication method thereof
    Patent number: 8872286
    Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: October 28, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Tsun-Min Cheng, Min-Chuan Tsai, Chih-Chien Liu, Jen-Chieh Lin, Pei-Ying Li, Shao-Wei Wang, Mon-Sen Lin, Ching-Ling Lin
  • Fin field-effect transistor structure
    Patent number: 8847325
    Abstract: A fin field-effect transistor structure comprises a substrate, a fin channel, a source/drain region, a high-k metal gate and a plurality of slot contact structures. The fin channel is formed on the substrate. The source/drain region is formed in the fin channel. The high-k metal gate formed on the substrate and the fin channel comprises a high-k dielectric layer and a metal gate layer, wherein the high-k dielectric layer is arranged between the metal gate layer and the fin channel. The slot contact structures are disposed at both sides of the metal gate.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: September 30, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • Sustained release implant for granisetron
    Patent number: 8835453
    Abstract: The main goals of the invention are to develop the long-term release of Granisetron injection implant composition with biodegradable polymer and to develop relative processing. Granisetron is mixed with different biodegradable polymers, and then hot melt extrusion technique with different diameter, temperature, rate of extrusion and holding time is applied to make implant. In vitro dissolution of the Granisetron injection implant composition shows the component continued release of the drug for over 7 days.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: September 16, 2014
    Assignee: Development Center for Biotechnology
    Inventors: Paonien Chan, Shou-Chung Chao, Shu-Chien Liu, Fan-Jung Liu, Li-Ya Wang
  • SEMICONDUCTOR PROCESS
    Publication number: 20140256115
    Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.
    Type: Application
    Filed: May 23, 2014
    Publication date: September 11, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Jei-Ming Chen, Jui-Min Lee, Yuh-Min Lin