Patents by Inventor Chien Liu

Chien Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and systems for media file management
    Patent number: 9201947
    Abstract: Methods and systems for media file management are provided. When a plurality of media files in the electronic device are viewed, media data is real-time generated for the media files. In the generation of the media data, the media files are analyzed to obtain a theme for the media files. Then, a script file is identified according to the theme, and media data is produced for the media files according to the script file. In some embodiments, a frame buffer used for storing the media data is refreshed after each frame of the media data is rendered.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 1, 2015
    Assignee: HTC CORPORATION
    Inventors: Chia-Fu Wu, Jenn-Wein Wu, Wen-Chien Liu, Jing-Lung Wu, Hsin-Ti Chueh, Ping-Yao Liao, David Folchi, Casaundra Meyers, Symon J. Whitehorn, Dennis Todd Harrington, Jorge Taketoshi Furuya Mariche, John Paul Stallard
  • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED BY THE SAME
    Publication number: 20150325574
    Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating deposition are substantially aligned with the top surface of the insulation.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 12, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Cheng Huang, Yu-Ting Li, Jen-Chieh Lin, Kun-Ju Li, Chang-Hung Kung, Yue-Han Wu, Chih-Chien Liu
  • Semiconductor structure with different fins of FinFETs
    Patent number: 9184292
    Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: November 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chun-Yuan Wu, Teng-Chun Tsai, Chih-Chien Liu
  • Semiconductor device having strained fin structure and method of making the same
    Patent number: 9184100
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: November 10, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
  • SPATIAL SEMICONDUCTOR STRUCTURE
    Publication number: 20150311284
    Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.
    Type: Application
    Filed: July 7, 2015
    Publication date: October 29, 2015
    Inventors: Hung-Lin SHIH, Chih-Chien LIU, Jei-Ming CHEN, Wen-Yi TENG, Chieh-Wen LO
  • Multigate field effect transistor and process thereof
    Patent number: 9159831
    Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: October 13, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Liu, Chun-Yuan Wu, Chin-Fu Lin, Chin-Cheng Chien, Chia-Lin Hsu
  • CAMERA DEVICE, VIDEO AUTO-TAGGING METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM THEREOF
    Publication number: 20150281567
    Abstract: A camera device, a video auto-tagging method and a non-transitory computer readable medium thereof are provided. The camera device comprises a processor, a camera and a sensor module. The camera is configured to capture a video. The sensor module is configured to generate distinctive sensing information after sensing a distinctive motion event of an user. The processor is configured to create a timing tag for the video according to the distinctive sensing information.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Applicant: HTC CORPORATION
    Inventors: Yuan-Mao TSUI, Yuan-Kang WANG, Wen-Chien LIU
  • SWITCHING DEVICE FOR USE IN A RATCHET WRENCH
    Publication number: 20150266171
    Abstract: A switching device includes a flow path unit, a control unit and a valve unit. The flow path unit includes an installation flow path, and a guide flow path communicating with an end portion of the installation flow path. The control unit includes a stem member movable within the installation flow path. The valve unit includes a valve member operable to permit compressed air to flow into the end portion of the installation flow path through the guide flow path or into an opposite end portion of the installation flow path for driving movement of the stem member along the installation flow path.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 24, 2015
    Inventors: Chun-Chi Lai, Chien-An Liu
  • Digitally controlled non-inverting buck-boost DC-DC converter system
    Patent number: 9122294
    Abstract: A digitally controlled non-inverting buck-boost DC-DC converter system including a non-inverting buck-boost DC-to-DC converter control module and a negative feedback module and applicable for a radio frequency circuit module is revealed. By locking a duty cycle to two specific levels, the non-inverting buck-boost DC-to-DC converter control module only needs a single operation mode to achieve the required effects. Simultaneously, pulse-skipping phenomenon is also avoided. Furthermore, a reference voltage is modified through a reference voltage correction circuit of the negative feedback module to eliminate errors between previous DC output voltage and the reference voltage. Thereby the DC output voltage can remain in a stable state so as to reduce operational defects during the mode transition.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: September 1, 2015
    Assignee: National Cheng Kung University
    Inventors: Han-Chien Liu, Chien-Hung Tsai, Yu-Shin Tsai
  • Spatial semiconductor structure and method of fabricating the same
    Patent number: 9105582
    Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: August 11, 2015
    Assignee: United Microelectronics Corporation
    Inventors: Hung-Lin Shih, Chih-Chien Liu, Jei-Ming Chen, Wen-Yi Teng, Chieh-Wen Lo
  • CONTROL METHOD FOR ACHIEVING POWER TRANSFER BETWEEN STACKED RECHARGEABLE BATTERY CELLS AND POWER TRANSFER CIRCUIT THEREOF
    Publication number: 20150222137
    Abstract: A control method for achieving power transfer between stacked rechargeable battery cells and a power transfer circuit are disclosed. The power transfer circuit includes an inductor, a first switch, a second switch and a controller. A loop of the rechargeable battery cell having higher power and the inductor is conducted so that the inductor stores power until the current flowing through the inductor meets the cutoff amount. Then, a loop of the rechargeable battery cell having lower power and the inductor is conducted so that the inductor releases the power saved in the inductor to the rechargeable battery cell having lower power until current flowing through the inductor changes direction. Therefore, balance between the rechargeable battery cells can be achieved.
    Type: Application
    Filed: February 4, 2014
    Publication date: August 6, 2015
    Applicant: HYCON TECHNOLOGY CORP.
    Inventors: Chuan Sheng WANG, Po Yin CHAO, Jui Chien LIU
  • Computer system and bootup and shutdown method thereof
    Patent number: 9098305
    Abstract: A computer system and a bootup and shutdown method thereof are provided. The computer system includes a memory, a chipset, a basic input/output system (BIOS), and an embedded controller, and an operating system (OS) is executed in the computer system. In the shutdown and bootup method, the embedded controller is notified to prepare to enter into a standby mode when the BIOS intercepts a shutdown instruction issued by the OS. The content of a register of the chipset is set according to the standby mode. A current operation mode data of the computer system is retained, and power is continuously supplied to the memory to make the computer system enter into the standby mode.
    Type: Grant
    Filed: May 30, 2011
    Date of Patent: August 4, 2015
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chih-Chien Liu, Feng-Hsun Chen, Chien-Ting Yeh
  • MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
    Publication number: 20150214114
    Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps. A substrate with a plurality of dummy gate structures formed thereon and a first dielectric layer covering the dummy gate structures is provided, the dummy gate structures comprising a plurality of dummy gates and a plurality of insulating layers formed on the dummy gates, wherein at least two of the dummy gate structures have different heights. A first planarization process is performed to expose at least one of the dummy gate structures having the highest height. A first etching process is performed to expose the insulating layers. A chemical mechanical polishing (CMP) process with a non-selectivity slurry is performed to planarize the dummy gate structures. The planarized dummy gate structures are removed to form a plurality of gate trenches.
    Type: Application
    Filed: January 28, 2014
    Publication date: July 30, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Po-Cheng Huang, Yu-Ting Li, Wu-Sian Sie, Yi-Liang Liu, Chun-Hsiung Wang, Kun-Ju Li, Chia-Lin Hsu, Chih-Chien Liu
  • METHOD FOR SWITCHING OPERATING SYSTEMS AND ELECTRONIC APPARATUS
    Publication number: 20150198999
    Abstract: A method for switching operating systems and an electronic apparatus are provided. A first operating system (OS) is notified to enter a power saving mode when a switching signal is received in case of running the first OS. In the power saving mode, a first running data of the first OS is stored to a first dump area of a storage unit from a system memory, a second OS is loaded to the system memory such that the second OS enters a normal operating mode.
    Type: Application
    Filed: March 28, 2014
    Publication date: July 16, 2015
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chih-Chien Liu, Chun-Sheng Chen
  • ALKALI-SOLUBLE RESIN COMPONENT AND PHOTOSENSITIVE RESIN COMPOSITION COMPRISING THE SAME
    Publication number: 20150175794
    Abstract: An alkali-soluble resin component includes a bisphenol fluorene-based resin, a quaternary ammonium salt compound, and a solvent. The quaternary ammonium salt compound is in an amount greater than 0.07 part by weight and smaller than 0.82 part by weight based on 100 parts by weight of the bisphenol fluorene-based resin.
    Type: Application
    Filed: July 16, 2014
    Publication date: June 25, 2015
    Inventor: Fu-Chien LIU
  • Semiconductor process
    Patent number: 9034726
    Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 19, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Jei-Ming Chen, Jui-Min Lee, Yuh-Min Lin
  • METHOD FOR FORMING A FINFET STRUCTURE
    Publication number: 20150132966
    Abstract: A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.
    Type: Application
    Filed: December 29, 2014
    Publication date: May 14, 2015
    Inventors: Hung-Lin Shih, Jei-Ming Chen, Chih-Chien Liu, Chin-Fu Lin, Kuan-Hsien Li
  • Method of fabricating semiconductor device
    Patent number: 9018087
    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 28, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu
  • METHOD OF FABRICATION TRANSISTOR WITH NON-UNIFORM STRESS LAYER WITH STRESS CONCENTRATED REGIONS
    Publication number: 20150087126
    Abstract: A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.) . Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.
    Type: Application
    Filed: December 2, 2014
    Publication date: March 26, 2015
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Yu-Shu Lin, Jei-Ming Chen, Wen-Yi Teng
  • METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20150064896
    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu