Patents by Inventor Chien Liu

Chien Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating FinFETs and semiconductor structure fabricated using the method
    Patent number: 8822284
    Abstract: A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: September 2, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chun-Yuan Wu, Teng-Chun Tsai, Chih-Chien Liu
  • Through-silicon via forming method
    Patent number: 8822336
    Abstract: A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: September 2, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • ATOMIC LAYER DEPOSITION METHOD
    Publication number: 20140242811
    Abstract: An ALD method includes providing a substrate in an ALD reactor, performing a pre-ALD treatment to the substrate in the ALD reactor, and performing one or more ALD cycles to form a dielectric layer on the substrate in the ALD reactor. The pre-ALD treatment includes providing a hydroxylating agent to the substrate in a first duration, and providing a precursor to the substrate in a second duration. Each of the ALD cycles includes providing the hydroxylating agent to the substrate in a third duration, and providing the precursor to the substrate in a fourth duration. The first duration is longer than the third duration.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jui-Chen Chang, Chen-Kuo Chiang, Chin-Fu Lin, Chih-Chien Liu
  • METHOD FOR FORMING ISOLATION STRUCTURE
    Publication number: 20140213034
    Abstract: A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer. A protective layer is formed to cover the trench and the hard mask layer. A first isolation material is filled into the trench. An etching process is performed to etch back part of the first isolation material.
    Type: Application
    Filed: January 29, 2013
    Publication date: July 31, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lung Chang, Chih-Chien Liu, Jei-Ming Chen, Wen-Yi Teng, Jui-Min Lee, Keng-Jen Lin, Chin-Fu Lin
  • PNEUMATIC RATCHET WRENCH CAPABLE OF PREVENTING MIS-SWITCHING OF ROTATIONAL DIRECTION
    Publication number: 20140202287
    Abstract: A pneumatic ratchet wrench includes a driving head, a feeding path, a primary path, a secondary path, a valve member, and a trigger. Upon flow of air into the primary path, the driving head is rotated. Upon flow of air into the secondary path, the rotational direction of the driving head can be switched. When the trigger is not actuated, the valve member is at a first position so as to prevent air to flow from the feeding path to the primary path, while allowing air to flow from the feeding path to the secondary path. When the trigger is actuated, the valve member is moved to a second position so as to allow air to flow from the feeding path to the primary path, while preventing air to flow from the feeding path to the secondary path.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 24, 2014
    Applicant: Basso Industry Corp.
    Inventors: Chun-Chi Lai, Chien-An Liu
  • Non-planar semiconductor structure
    Patent number: 8779513
    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: July 15, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Hung Tsai, Chien-Ting Lin, Chin-Cheng Chien, Chin-Fu Lin, Chih-Chien Liu, Teng-Chun Tsai, Chun-Yuan Wu
  • Semiconductor structure and process thereof
    Patent number: 8772904
    Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: July 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Jei-Ming Chen, Jui-Min Lee, Yuh-Min Lin
  • MULTICOLOR THERMAL IMAGING METHOD AND THERMAL PRINTER
    Publication number: 20140187418
    Abstract: A multicolor direct thermal imaging method wherein a multicolor image is formed in a thermal imaging member comprising at least first and second different image-forming compositions and a thermal printer for use in practicing the method. Heat is applied to at least the second image-forming composition while the first image-forming composition is at a first baseline temperature (T1) to form an image in at least the second image-forming composition, and heat is applied to at least the first image-forming composition while it is at a second baseline temperature (T2) to form an image in at least the first image-forming composition, wherein T1 is different from T2.
    Type: Application
    Filed: August 6, 2013
    Publication date: July 3, 2014
    Applicant: Zink Imaging, Inc.
    Inventors: Brian D. Busch, Fariza B. Hasan, Chien Liu, Stephen J. Telfer, William T. Vetterling
  • COMPUTER READABLE STORAGE MEDIUM FOR STORING APPLICATION PROGRAM FOR NETWORK CERTIFICATION
    Publication number: 20140181996
    Abstract: The present invention discloses a computer readable storage medium for storing an application program for network certification. The application program is implemented by an electrical device to execute a network certification process. The network certification process includes the following steps: a network module of the electrical device is driven to receive a certification code, which is broadcasted by a network access point (AP). Determine if the certification code is in an identified list. When the certification code is not in the identified list, the application program executes an action to limit communication between the electrical device and the network AP.
    Type: Application
    Filed: March 27, 2013
    Publication date: June 26, 2014
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chih-Chien LIU, Yi-Chang CHEN, Chih-Hsing KANG
  • Apparatuses and methods for providing multi-standby mode of wireless communications using single subscriber identity card with multiple subscriber numbers
    Patent number: 8755841
    Abstract: A communication device is provided with a processing unit. The processing unit reads a plurality of elementary files from a single subscriber identity card for each of a plurality of subscriber numbers when power-on, and registers to a network for each of the subscriber numbers according to the read elementary files. Also, the processing unit enables a multi-standby mode of wireless communications in response to successful registration to the network for at least two of the subscriber numbers.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: June 17, 2014
    Assignee: Mediatek Inc.
    Inventors: Chih-Hung Lee, Min-Ju Wu, Nai-Hsin Chang, Jen-Chien Liu
  • APPARATUSES AND METHODS FOR PROVIDING MULTI-STANDBY MODE OF WIRELESS COMMUNICATIONS USING SINGLE SUBSCRIBER IDENTITY CARD WITH MULTIPLE SUBSCRIBER NUMBERS
    Publication number: 20140135066
    Abstract: A communication device is provided with a processing unit. The processing unit determines whether at least one elementary file in a single subscriber identity card is required to be read out. If so, the processing unit activates one subscriber identity module instance in the subscriber identity card for the elementary file, and reads the elementary file from the subscriber identity card.
    Type: Application
    Filed: January 21, 2014
    Publication date: May 15, 2014
    Applicant: MediaTek Inc.
    Inventors: Chih-Hung LEE, Min-Ju WU, Nai-Hsin CHANG, Jen-Chien LIU
  • METHOD OF FABRICATING DIELECTRIC LAYER AND SHALLOW TRENCH ISOLATION
    Publication number: 20140134824
    Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 15, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jei-Ming Chen, Wen-Yi Teng, Chia-Lung Chang, Chih-Chien Liu
  • APPARATUSES AND METHODS FOR PROVIDING MULTI-STANDBY MODE OF WIRELESS COMMUNICATIONS USING SINGLE SUBSCRIBER IDENTITY CARD WITH MULTIPLE SUBSCRIBER NUMBERS
    Publication number: 20140135065
    Abstract: A communication device is provided with a processing unit. The processing unit reads a plurality of elementary files from a single subscriber identity card for each of a plurality of subscriber numbers when power-on, and registers to a network for each of the subscriber numbers according to the read elementary files. Also, the processing unit enables a multi-standby mode of wireless communications in response to successful registration to the network for at least two of the subscriber numbers.
    Type: Application
    Filed: January 21, 2014
    Publication date: May 15, 2014
    Applicant: MediaTek Inc.
    Inventors: Chih-Hung LEE, Min-Ju WU, Nai-Hsin CHANG, Jen-Chien LIU
  • MULTIGATE FIELD EFFECT TRANSISTOR AND PROCESS THEREOF
    Publication number: 20140117455
    Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 1, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Liu, Chun-Yuan Wu, Chin-Fu Lin, Chin-Cheng Chien, Chia-Lin Hsu
  • Method of forming an isolation structure
    Patent number: 8709901
    Abstract: The present invention relates to a method of forming an isolation structure, in which, a trench is formed in a substrate through a hard mask, and deposition, etch back, deposition, planarization, and etch back are performed in the order to form an isolation material layer of the isolation structure after the hard mask is removed. A silicon layer may be formed to cover the trench and original surface of the substrate before the former deposition, or to cover a part of the trench and original surface of the substrate after the former etch back and before the later deposition, to serve as a stop layer for the planarization process. Voids existing within the isolation material layer can be exposed or removed by partially etching the isolation material layer by the former etch back. The later deposition can be performed with a less aspect ratio to avoid forming voids.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: April 29, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Lung Chang, Wu-Sian Sie, Jei-Ming Chen, Wen-Yi Teng, Chih-Chien Liu, Jui-Min Lee, Chih-Hsun Lin
  • METHOD OF FORMING OPENING ON SEMICONDUCTOR SUBSTRATE
    Publication number: 20140106568
    Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 17, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Po-Chun Chen
  • TRANSISTOR
    Publication number: 20140091395
    Abstract: A method for fabricating a transistor device including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a lower tensile stress than the second tensile stress layer.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 3, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Yu-Shu Lin, Jei-Ming Chen, Wen-Yi Teng
  • DIGITALLY CONTROLLED NON-INVERTING BUCK-BOOST DC-DC CONVERTER SYSTEM
    Publication number: 20140077870
    Abstract: A digitally controlled non-inverting buck-boost DC-DC converter system including a non-inverting buck-boost DC-to-DC converter control module and a negative feedback module and applicable for a radio frequency circuit module is revealed. By locking a duty cycle to two specific levels, the non-inverting buck-boost DC-to-DC converter control module only needs a single operation mode to achieve the required effects. Simultaneously, pulse-skipping phenomenon is also avoided. Furthermore, a reference voltage is modified through a reference voltage correction circuit of the negative feedback module to eliminate errors between previous DC output voltage and the reference voltage. Thereby the DC output voltage can remain in a stable state so as to reduce operational defects during the mode transition.
    Type: Application
    Filed: January 9, 2013
    Publication date: March 20, 2014
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: HAN-CHIEN LIU, CHIEN-HUNG TSAI, YU-SHIN TSAI
  • METHODS AND SYSTEMS FOR MEDIA FILE MANAGEMENT
    Publication number: 20140081975
    Abstract: Methods and systems for media file management are provided. When a plurality of media files in the electronic device are viewed, media data is real-time generated for the media files. In the generation of the media data, the media files are analyzed to obtain a theme for the media files. Then, a script file is identified according to the theme, and media data is produced for the media files according to the script file. In some embodiments, a frame buffer used for storing the media data is refreshed after each frame of the media data is rendered.
    Type: Application
    Filed: March 18, 2013
    Publication date: March 20, 2014
    Applicant: HTC CORPORATION
    Inventors: Chia-Fu WU, Jenn-Wein WU, Wen-Chien LIU, Jing-Lung WU, Hsin-Ti CHUEH, Ping-Yao LIAO, David FOLCHI, Casaundra MEYERS, Symon J. WHITEHORN, Dennis Todd HARRINGTON, Jorge Taketoshi Furuya MARICHE, John Paul STALLARD
  • FABRICATION METHOD FOR SEMICONDUCTOR DEVICES
    Publication number: 20140065775
    Abstract: A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 6, 2014
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chia-Lin Hsu