Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a drain positioned in the substrate; a top dielectric layer positioned on the substrate; a cell contact structure including a cell contact bottom conductive layer positioned in the top dielectric layer and on the drain, a cell contact top conductive layer positioned in the top dielectric layer and on the cell contact bottom conductive layer, and a cell contact top sealing layer positioned in the top dielectric layer, on the cell contact bottom conductive layer, and surrounding the cell contact top conductive layer; and a first air gap positioned in the top dielectric layer and surrounding the cell contact bottom conductive layer.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: Embodiments of the present disclosure provide methods for forming merged source/drain features from two or more fin structures. The merged source/drain features according to the present disclosure have a merged portion with an increased height percentage over the overall height of the source/drain feature. The increase height percentage provides an increased landing range for source/drain contact features, therefore, reducing the connection resistance between the source/drain feature and the source/drain contact features. In some embodiments, the emerged source/drain features include one or more voids formed within the merged portion.

Abstract: A semiconductor device includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell operatively arranged along a first one of a plurality of columns, and operatively arranged in a first one, a second one, a third one, and a fourth one of a plurality of rows, respectively. The first column operatively corresponds to a first pair of bit lines and a second pair of bit lines. The first to fourth rows operatively correspond to a first word line, a second word line, a third word line, and a fourth word line, respectively. The first pair of bit lines are operatively coupled to the first and second memory cells. The second pair of bit lines are operatively coupled to the third and fourth memory cells.

Abstract: A method of making a semiconductor device includes forming a first device on a first side of a substrate, wherein the first device comprises a first source/drain (S/D) electrode. The method further includes forming a second device on a second side of the substrate, wherein the second side of the substrate is opposite the first side of the substrate, and the second device comprises a second S/D electrode. The method further includes forming a through substrate via (TSV) electrically connecting the first S/D electrode to the second S/D electrode, wherein a width of the TSV is equal to a width of at least one of the first S/D electrode or the second S/D electrode.

Abstract: A method includes forming, over a substrate, adjacent first and second transistor stacks each including a first transistor, and a second transistor over the first transistor. A plurality of first conductive lines is formed in a first metal layer. The plurality of first conductive lines includes a power conductive line configured to route power to the first transistor stack, one or more signal conductive lines configured to route one or more signals to the first transistor stack, and a shielding conductive line configured to shield the routed one or more signals. The power conductive line or the shielding conductive line is shared with the second transistor stack.

Abstract: A fan module includes a mounting bracket, a fan and a one-way shutter are detachably installed in the mounting bracket. The fan module is configured for installation at an electronic device along an insertion direction, the fan is configured to generate airflow along or opposite to the insertion direction, and the one-way shutter allows the airflow to pass through. The fan is configured to generate airflow in an opposite direction by being turned over, and the one-way shutter allows the airflow in the opposite direction to pass through by being turned over correspondingly. The one-way shutter includes a shutter base defining multiple guide holes, a baffle, and multiple float balls in the guide holes for allowing or preventing air to pass through the guide holes to achieve one-way pass function. An electronic device comprising the fan module is also provided.

Abstract: A method for performing transmission power control of a wireless transceiver device in wireless communications system and associated apparatus are provided. The method may include: obtaining at least one indicator regarding a current channel, for channel detection of the current channel; detecting the current channel based on the at least one indicator to generate at least one channel detection result, wherein when one of the at least one channel detection result indicates a current channel model of the current channel, the current channel model is one of multiple predetermined channel models; and determining at least one transmission power value according to the at least one channel detection result, for performing packet transmission with the at least one transmission power value.

Abstract: A fan module includes a mounting bracket, a fan and an anti-backflow device are detachably installed in the mounting bracket. The fan is configured to generate airflow along a predetermined direction, and the anti-backflow device allows the airflow to pass through. The fan is configured to generate airflow in another direction by being turned over, and the anti-backflow device allows the airflow in another direction to pass through be being turned over correspondingly. The anti-backflow device includes a louver assembly for one-way pass function. An electronic device comprising the fan module is also provided.

Abstract: A method includes fabricating a first-type active-region semiconductor structure and second-type active-region semiconductor structure stacked with each other. The method also includes fabricating an upper source conductive segment intersecting the second-type active-region semiconductor structure at a second source region and forming a front-side power rail extending in a first direction that is conductively connected to the upper source conductive segment through a front-side terminal via-connector. The method further includes forming a top-to-bottom via-connector that passes through the substrate and conductively connects to the upper source conductive segment, forming a back-side metal layer on a backside of the substrate, and forming a back-side power node extending in the first direction that is conductively connected to the top-to-bottom via-connector.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: A method of fabricating an integrated circuit includes fabricating a set of transistors in a front-side of a substrate, depositing a first conductive material over the set of transistors on a first level thereby forming a set of contacts for the set of transistors, fabricating a first set of vias over the set of transistors, depositing a second conductive material over the set of contacts on a second level thereby forming a set of power rails, depositing a third conductive material over the set of contacts on the second level thereby forming a first set of conductors, and depositing a fourth conductive material over the set of contacts on the second level thereby forming a second set of conductors. The set of power rails and the first set of conductors have the first width. The second set of conductors has a second width different from the first width.

Abstract: A method of decoding a bitstream by an electronic device is provided. The method receives an image frame of a bitstream and determines a block unit having a block width and a block height based on the received image frame. The method determines whether a geometric partitioning mode is disabled for the block unit based on a comparison between the block width and the block height. The method divides the block unit to generate multiple sub-blocks predicted by different merge candidates of the block unit when the geometric partitioning mode is enabled and applied on the block unit. The predicted block is generated by predicting block unit based on a prediction mode different from the geometric partitioning mode when the geometric partitioning mode is disabled for the block unit. The method them reconstructs the block unit based on the predicted block.

Abstract: Embodiments include structures and methods for fabricating an MFM capacitor having a plurality of metal contacts. An embodiment may include a first metal strip, disposed on a substrate and extending in a first direction, a ferroelectric blanket layer, disposed on the first metal strip, a second metal strip, disposed on the ferroelectric blanket layer and extending in a second direction different from the first direction, and a plurality of metal contacts disposed between the first metal strip and the second metal strip and located within an intersection region of the first metal strip and the second metal strip.

Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided. The semiconductor substrate includes a logic circuit. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the logic circuit, and the interconnect structure includes stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers. The memory cell array is embedded in the stacked interlayer dielectric layers. The memory cell array includes driving transistors and memory devices, and the memory devices are electrically connected the driving transistors through the interconnect wirings.

Abstract: A semiconductor device and related method for forming a gate structure. In some embodiments, a semiconductor device includes a fin extending from a substrate. In some cases, the fin includes a plurality of semiconductor channel layers. In some examples, the semiconductor device further includes a gate dielectric surrounding each of the plurality of semiconductor channel layers. In some embodiments, a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.

Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; two adjacent radiation-sensing regions formed in the substrate; and a trench isolation structure extending from the back surface of the substrate into the substrate between the two adjacent radiation-sensing regions. The trench isolation structure includes: a dielectric material; a first film being formed between the dielectric material and the substrate; a second film being formed between the first film and the dielectric material; and a third film being formed between the second film and the dielectric material. An electronegativity of the first film, an electronegativity of the second film and an electronegativity of the third film are different from each other.

Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided. The semiconductor substrate includes a logic circuit. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the logic circuit, and the interconnect structure includes stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers. The memory cell array is embedded in the stacked interlayer dielectric layers. The memory cell array includes driving transistors and memory devices, and the memory devices are electrically connected the driving transistors through the interconnect wirings.

Abstract: A memory device includes a conductive segment, first and second rows of memory cells. The conductive segment receives a first reference voltage signal. The first row of memory cells is coupled to a first word line. The second row of memory cells is coupled to a second word line. The first row of memory cells includes first and second memory cells. The first memory cell is coupled to the conductive segment to receive the first reference voltage signal. The second row of memory cells includes third and fourth memory cells. The third memory cell is coupled to the conductive segment to receive the first reference voltage signal. The first and third memory cells share the conductive segment, and the third memory cell is arranged between the first and second memory cells. The second memory cell is arranged between the third and fourth memory cells.

Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.