Abstract: The present invention provides improved driving methods for four particle electrophoretic displays that improves the performance of such displays when they are deployed in low temperature environments and the displays are required to be updated when positioned vertically (i.e., the driving electric fields are substantially perpendicular to the direction of Earth's gravity). Methods are provided for displaying each of the colors at each pixel, as desired, with minimal interference (contamination) from the other particles.

Abstract: A method of encoding video data by an electronic device is provided. The electronic device determines whether an affine enabled flag corresponding to one or more image frames included in the video data is true. The electronic device determines a maximum number of zero or more subblock-based merging motion vector prediction candidates corresponding to the one or more image frames when the affine enabled flag is true. The maximum number is in a number range of K to N, N being a first integer and K being a second integer less than N. The electronic device determines that a maximum index is in an index range of 0 to N-K and generated by subtracting the maximum number from N when the affine enabled flag is true. An index value of the maximum index is in an index range of 0 to N-1 when K is 1.

Abstract: The present invention provides four-particle electrophoretic displays with improved driving methods to achieve better color separation between adjacent pixel electrodes. The driving methods improve the color state performance when a first pixel is displaying a mixed state of a first highly-charged particle and a second lower-charged particle of the opposite polarity, while a neighboring pixel is displaying a state of a second highly-charged particle having the opposite polarity to the first highly-charged particle. The particles can be, for example, all reflective or one type of particle can be partially light transmissive.

Abstract: The present invention discloses a microwave heating system for desorbing contaminated soil, comprising: a feeding module; a heating cavity; a first microwave suppression cavity; a second microwave suppression cavity; a conveyor belt; a feeding device; and an exhaust module. The feeding device is arranged above the first microwave suppression cavity or the second microwave suppression cavity, and the feeding device contains a microwave absorber material. The invention further discloses a microwave heating process for desorption of polluted soil. With the microwave heating system and process for desorbing contaminated soil, the contaminated soil can be heated quickly and uniformly, and quickly cooled and taken out smoothly.

Abstract: Compounds, compositions and methods are provided for modulating the activity of EP2 and EP4 receptors, and for the treatment, prevention and amelioration of one or more symptoms of diseases or disorders related to the activity of EP2 and EP4 receptors. In certain embodiments, the compounds are antagonists of both the EP2 and EP4 receptors.

Abstract: A memory device includes a plurality of memory cells disposed over a substrate and formed as an array that has a plurality of rows and a plurality of columns. Each of the plurality of memory cells includes a plurality of transistors. A first subset of the plurality of memory cells, that are disposed in first neighboring ones of the plurality of rows, are physically coupled to a corresponding one of a plurality of second interconnect structures that carries a supply voltage through a corresponding one of a plurality of first interconnect structures. The plurality of first interconnect structures extend along a first lateral direction in parallel with a lengthwise direction of a channel of each of the transistors of the memory cells, and the plurality of second interconnect structures, disposed above the plurality of first interconnect structures, extend along a second lateral direction perpendicular to the first lateral direction.

Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

Abstract: A method of decoding video data performed by an electronic device is provided. The method receives the video data and determines a block unit from a current frame included in the video data. The method further determines a plurality of luma reconstructed samples in a luma block of the block unit based on the video data and determines a prediction model filter of a prediction model mode for a chroma block of the block unit based on the video data. The method then determines a prediction model filter of a prediction model mode for a chroma block of the block unit based on the video data and reconstruct the chroma block of the block unit by applying the plurality of luma square values and the plurality of luma gradient values to the prediction model filter.

Abstract: A power conversion device includes a conversion device having includes a first, a second, a third and a fourth converter, and a control unit. The first converter has a first input terminal and a first output terminal; the second converter has a second input terminal and a second output terminal; the first and the second input terminal are electrically connected to a power supply. The third converter has a third input terminal and a third output terminal, the third input terminal is coupled to the first output terminal; the fourth converter has a fourth input terminal and a fourth output terminal; the fourth input terminal is coupled to the second output terminal, and the third output terminal is electrically connected to the fourth output terminal. The control unit is coupled to the conversion device, receives a power request from a load, and controls an output power of the conversion device.

Abstract: A power conversion device used in electric vehicles includes a transmission assembly and a power converter. The transmission assembly is detachably connected to the electric vehicle and receives a first power from the battery pack of the electric vehicle. The power converter is electrically connected to the transmission assembly and converts the first power into a second power or a third power. The power converter is configured outside the electric vehicle.

Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. In some embodiments, the FeFET device includes a ferroelectric layer having a first side and a second side opposite to the first side and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device further includes an OS channel layer disposed along the second side of the ferroelectric layer opposite to the first side and a pair of source/drain regions disposed on opposite sides of the OS channel layer. The FeFET device further includes a 2D contacting layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contacting layer has a second doping type different than the first doping type.

Abstract: A compact optical imaging device with short optical length and low sensitivity, for use in an imaging module and an electronic device, comprises first to fifth lenses and a filter. An image-side surface of the fourth lens is convex near an optical axis of the optical imaging device. An image-side surface of the fifth lens is concave near the optical axis. The optical imaging device satisfies formulas 0.03 mm/°<TL5/FOV<0.1 mm/° and 2.4 mm<TL4/FNO<2.9 mm, TL5 being a distance from an object-side surface of the fifth lens to an image plane of the optical imaging device along the optical axis, FOV being a maximum field of view, TL4 being a distance from an object-side surface of the fourth lens to the image plane along the optical axis, and FNO being a F-number of the optical imaging device.

Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: Disclosed herein are related to a memory device. In one aspect, a memory device includes a set of memory cells. In one aspect, the memory device includes a first bit line extending along a direction. The first bit line may be coupled to a subset of the set of memory cells disposed along the direction. In one aspect, the memory device includes a second bit line extending along the direction. In one aspect, the memory device includes a switch coupled between the first bit line and the second bit line.

Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.

Abstract: A laryngoscope is provided and includes a handle, a blade assembly and a plurality of light emitting components. The blade assembly includes a supporting body and a sleeve body. The supporting body is pivotally connected to the handle. The sleeve body is sleeved outside the supporting body. The plurality of light emitting components are disposed on the supporting body and arranged in an arc shape on a first flat plane. Besides, at least one light divergence structure is optionally formed on the sleeve body for diverging light emitted from the plurality of light emitting components, and the supporting body optionally includes a supporting component and a heat dissipating component for conducting heat generated by the plurality of light emitting components to the supporting component. Therefore, the present invention can not only provide bright and wide illumination but also have anti-fogging function.

Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate and a metallization structure over the substrate. The metallization structure includes a MIM structure, a first contact and a second contact. The MIM structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, and a top electrode layer on the ferroelectric layer. The ferroelectric layer is substantially made of lead zirconate titanate (PZT), BaTiO3 (BTO), or barium strontium titanate (BST), and a thickness of the ferroelectric layer is greater than a thickness of the dielectric layer.

Abstract: An integrated circuit includes a first conductor segment intersecting a first active-region structure at a source/drain region and a second conductor segment intersecting a second active-region structure at a source/drain region. The first conductor segment and the second conductor segment are separated at proximal edges by a separation distance. A distance from a first horizontal cell boundary to a proximal edge of the first conductor segment is larger than a distance from a second horizontal cell boundary to a proximal edge of the second conductor segment by a predetermined distance that is a fraction of the separation distance.

Abstract: A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.