Patents by Inventor Chih Yu
Chih Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12025637Abstract: The present invention provides a probe card comprising a probe base, at least one impedance-matching probes, and a plurality of first probes. The probe base has a probing side and a tester side opposite to the probing side. Each impedance-matching probe has a probing part and a signal transmitting part electrically coupled to the probing part, wherein one end of the signal transmitting part is arranged at tester side, and the signal transmitting part has a central probing axis. Each first probe has a probing tip and a cantilever part coupled to the probing tip, wherein the cantilever part is coupled to the probe base and has a first central axis such that an included angle is formed between the central probing axis and the first central axis.Type: GrantFiled: October 13, 2021Date of Patent: July 2, 2024Assignee: MPI CORPORATIONInventors: Chin-Yi Tsai, Chia-Tai Chang, Cheng-Nien Su, Chin-Tien Yang, Chen-Chih Yu
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Patent number: 12029023Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull down transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact. The first metal contact layout pattern overlaps the cell boundary of the memory circuit and the first active region layout pattern. The first metal contact electrically coupled to a source of the first pull down transistor. The memory circuit being a four transistor (4T) memory cell including a first and second pass gate transistor, and a first and second pull down transistor.Type: GrantFiled: April 20, 2023Date of Patent: July 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Yen-Huei Chen, Hung-Jen Liao
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Publication number: 20240210995Abstract: A display may have a stretchable portion with hermetically sealed rigid pixel islands. A flexible interconnect region may be interposed between the hermetically sealed rigid pixel islands. The hermetically sealed rigid pixel islands may include organic light-emitting diode (OLED) pixels. A conductive cutting structure may have an undercut that causes a discontinuity in a conductive OLED layer to mitigate lateral leakage. The conductive cutting structure may also be electrically connected to a cathode for the OLED pixels and provide a cathode voltage to the cathode. First and second inorganic passivation layers may be formed over the OLED pixels. Multiple discrete portions of an organic inkjet printed layer may be interposed between the first and second inorganic passivation layers.Type: ApplicationFiled: October 10, 2023Publication date: June 27, 2024Inventors: Prashant Mandlik, Bhadrinarayana Lalgudi Visweswaran, Mahendra Chhabra, Chia-Hao Chang, Shiyi Liu, Siddharth Harikrishna Mohan, Zhen Zhang, Han-Chieh Chang, Yi Qiao, Yue Cui, Tyler R Kakuda, Michael Vosgueritchian, Sudirukkuge T. Jinasundera, Warren S Rieutort-Louis, Tsung-Ting Tsai, Jae Won Choi, Jiun-Jye Chang, Jean-Pierre S Guillou, Rui Liu, Po-Chun Yeh, Chieh Hung Yang, Ankit Mahajan, Takahide Ishii, Pei-Ling Lin, Pei Yin, Gwanwoo Park, Markus Einzinger, Martijn Kuik, Abhijeet S Bagal, Kyounghwan Kim, Jonathan H Beck, Chiang-Jen Hsiao, Chih-Hao Kung, Chih-Lei Chen, Chih-Yu Chung, Chuan-Jung Lin, Jung Yen Huang, Kuan-Chi Chen, Shinya Ono, Wei Jung Hsieh, Wei-Chieh Lin, Yi-Pu Chen, Yuan Ming Chiang, An-Di Sheu, Chi-Wei Chou, Chin-Fu Lee, Ko-Wei Chen, Kuan-Yi Lee, Weixin Li, Shin-Hung Yeh, Shyuan Yang, Themistoklis Afentakis, Asli Sirman, Baolin Tian, Han Liu
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Publication number: 20240213367Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. In some embodiments, the FeFET device includes a ferroelectric layer having a first side and a second side opposite to the first side and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device further includes an OS channel layer disposed along the second side of the ferroelectric layer opposite to the first side and a pair of source/drain regions disposed on opposite sides of the OS channel layer. The FeFET device further includes a 2D contacting layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contacting layer has a second doping type different than the first doping type.Type: ApplicationFiled: March 7, 2024Publication date: June 27, 2024Inventors: Mauricio Manfrini, Chih-Yu Chang, Sai-Hooi Yeong
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Publication number: 20240212749Abstract: A memory device and a method for operating the memory device are provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.Type: ApplicationFiled: March 11, 2024Publication date: June 27, 2024Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
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Publication number: 20240213102Abstract: A method for detecting a seam in a film is provided. The following process is performed on a film in a first wafer: (a) a scan is performed to obtain a gray level image; (b) a region positioning process is performed on the gray level image to define target regions and a seam region located in each target region; (c) a gray level value of each pixel in each seam region is obtained, and the number of pixels whose gray level values are lower than a gray level threshold value in each seam region is calculated; (d) a pixel quantity threshold value is generated according to the number in each seam region. Then, the process (a) to (c) is performed on a film in a second wafer, and a seam region having the number exceeding the pixel quantity threshold value is determined to be a defect region.Type: ApplicationFiled: December 26, 2023Publication date: June 27, 2024Applicant: Winbond Electronics Corp.Inventors: Chih-Yu Chiang, Chi-Hung Chan
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System and method for prediction of intradialytic adverse event and computer readable medium thereof
Patent number: 12020812Abstract: Provided are a system and a method for prediction of an intradialytic adverse event, where a machine learning model of two-class classification is utilized to predict intradialytic adverse events in quasi-real time, such that features extracted in an ongoing hemodialysis process in real time can have the hemodialysis session alerted for forthcoming adverse events. Therefore, clinicians can be warned to take necessary actions and adjust the hemodialysis machine settings in advance. In addition, a computer readable medium thereof is also provided.Type: GrantFiled: September 29, 2021Date of Patent: June 25, 2024Assignee: National Yang Ming Chiao Tung UniversityInventors: Oscar Kuang-Sheng Lee, Chih-Yu Yang, Yi-Shiuan Liu -
Patent number: 12022643Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.Type: GrantFiled: September 29, 2020Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Yu-Chia Liang, Shih-Hao Lin, Kuei-Lun Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20240203488Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.Type: ApplicationFiled: February 28, 2024Publication date: June 20, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hidehiro FUJIWARA, Chih-Yu LIN, Sahil Preet Singh, Hsien-Yu PAN, Yen-Huei CHEN, Hung-Jen LIAO
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Publication number: 20240206185Abstract: The present disclosure relates to an integrated chip device. The integrated chip device includes a plurality of conductive lines disposed over a substrate. The plurality of conductive lines are stacked onto one another and are separated from one another by dielectric layers interleaved between adjacent ones of the plurality of conductive lines. A ferroelectric layer is along sidewalls of the plurality of conductive lines and the dielectric layers. The ferroelectric layer separates a channel layer from the plurality of conductive lines. A species is disposed within the ferroelectric layer. The species has a concentration that decreases from the channel layer towards a surface of the ferroelectric layer that faces away from the channel layer.Type: ApplicationFiled: February 29, 2024Publication date: June 20, 2024Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chih-Yu Chang
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Patent number: 12009362Abstract: A method of making a semiconductor device includes forming a first active region on a first side of a substrate. The method further includes forming a first source/drain (S/D) electrode surrounding a first portion of the first active region. The method further includes forming an S/D connect via extending through the substrate. The method further includes flipping the substrate. The method further includes forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. The method further includes forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.Type: GrantFiled: July 27, 2023Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Yu Lai, Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang, Ching-Wei Tsai, Shang-Wen Chang
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Publication number: 20240186414Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.Type: ApplicationFiled: January 2, 2024Publication date: June 6, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Ming LIN, Sai-Hooi YEONG, Ziwei FANG, Bo-Feng YOUNG, Chi On CHUI, Chih-Yu CHANG, Huang-Lin CHAO
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Publication number: 20240186415Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.Type: ApplicationFiled: February 13, 2024Publication date: June 6, 2024Inventors: Chih-Yu Ma, Shahaji B. More, Yi-Min Huang, Shih-Chieh Chang
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Publication number: 20240179334Abstract: A non-transitory medium of a device that stores instructions is provided. The instructions, when executed by a processing unit of the device, cause the device to: receive first motion information having a first list flag for a first reference frame and second motion information having a second list flag for a second reference frame for a block unit; compare the two list flags when a sub-block is included in a specific one of block regions covering a split line of the block unit; store a predefined one of the first and the second motion information for the sub-block without checking whether the two reference frames are included in a list indicated by a value different from the two list flags when the two list flags are the same; and store the first and the second motion information together for the sub-block when the two list flags are different.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Chih-Yu Teng, Yu-Chiao Yang, Po-Han Lin
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Patent number: 11996484Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.Type: GrantFiled: May 13, 2021Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
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Patent number: 11997854Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: receiving a substrate; forming a transistor surrounded by a dielectric layer over the substrate, wherein the dielectric layer includes a through hole, and the transistor is formed in the through hole; forming a gate contact in the through hole to electrically connect the transistor; forming a ferroelectric layer over the gate contact in the through hole; forming an insulating layer conformal to and over the dielectric layer and the ferroelectric layer; removing a portion of the insulating layer to form a spacer in the through hole and over the ferroelectric layer; and forming a top electrode over the ferroelectric layer and between the spacer.Type: GrantFiled: May 20, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chih-Yu Chang, Sai-Hooi Yeong, Yu-Ming Lin, Chih-Hao Wang
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Publication number: 20240172433Abstract: A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.Type: ApplicationFiled: February 1, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Feng YOUNG, Sai-Hooi YEONG, Chih-Yu CHANG, Han-Jong CHIA, Chenchen Jacob WANG, Yu-Ming LIN
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Publication number: 20240170230Abstract: A method for prelithiating a soft carbon negative electrode includes the steps of: disposing the soft carbon negative electrode and a lithium metal piece spaced apart from each other with a lithium-containing electrolyte present therebetween; prelithiating the soft carbon negative electrode at a first constant C-rate until a voltage thereof is reduced to a first predetermined voltage not greater than 0.3 V vs. Li/Li+, the first constant C-rate being not greater than 5 C; prelithiating the soft carbon negative electrode at a second constant C-rate until the voltage thereof is reduced to a second predetermined voltage lower than the first predetermined voltage, the second constant C-rate being not greater than 0.2 C and being less than the first constant C-rate; and prelithiating the soft carbon negative electrode at a prelithiation constant voltage which is not greater than the second predetermined voltage, thereby completing prelithiation of the soft carbon negative electrode.Type: ApplicationFiled: January 13, 2023Publication date: May 23, 2024Inventors: Yan-Shi CHEN, Guo-Hsu LU, Chi-Chang HU, Chih-Yu KU, Tien-Yu YI
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Patent number: 11989077Abstract: A management circuit is coupled to multiple processor cores for performing current suppression. The management circuit includes a detection circuit and a throttle signal generator. The detection circuit is operative to receive an activity signal from each processor core, and estimate a total current consumed by the plurality of processor cores based on activity signals. The activity signal indicates a current index proportional to current consumption of the processor core in a given time period. The throttle signal generator is operative to assert or de-assert throttle signals to the processor cores, one processor core at a time, based on one or more metrics calculated from the total current.Type: GrantFiled: July 16, 2022Date of Patent: May 21, 2024Assignee: MediaTek Inc.Inventors: Hung-Wei Wu, Chih-Yu Chang
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Patent number: 11991888Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.Type: GrantFiled: June 29, 2023Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Chih-Yu Chang, Han-Jong Chia, Sai-Hooi Yeong, Yu-Ming Lin
