Abstract: Techniques pertaining to trigger-based (TB) implicit feedback for implicit beamforming in wireless communications are described. An apparatus (e.g., an access point (AP)) triggers each of one or more stations (STAs) to transmit a respective feedback. The apparatus estimates a respective steering matrix with respect to each of the one or more STAs based on the respective feedback. The apparatus then transmits a respective steered data to each of the one or more STAs based on the respective steering matrix.

Abstract: A columnar illumination component includes a columnar body and a light-emitting component. The columnar body has two first side portions, and two second side portions. Each of the first side portions is adjoined to the second side portions, each of the second side portions is adjoined to the first side portions, and an elongated channel is jointly defined by the first side portions and the second side portions. The light-emitting component is located inside the elongated channel, and includes two light guides and two light source modules where the light guides are respectively fixed on the first side portions. The light source modules are respectively fixed on the second side portions, and each of the light source modules emits lights towards one of the light guides, and outputs the lights outwardly through the light guide.

Abstract: A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: A resistor structure includes a resistor body; and a first electrode structure disposed at and being in electric contact with a first end of the resistor body, and a second electrode structure disposed at and being in electric contact with a second end opposite to the first end of the resistor body. Each of the first electrode structure and the second electrode structure has at least one conductive protrusion. The at least one conductive protrusion of the first electrode structure and the at least one conductive protrusion of the second electrode structure both serve as voltage-sensing terminals for electric connection to an external voltage measurement device, or both serve as current-sensing terminals for electric connection to a current measurement device.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: receiving a substrate; forming a transistor surrounded by a dielectric layer over the substrate, wherein the dielectric layer includes a through hole, and the transistor is formed in the through hole; forming a gate contact in the through hole to electrically connect the transistor; forming a ferroelectric layer over the gate contact in the through hole; forming an insulating layer conformal to and over the dielectric layer and the ferroelectric layer; removing a portion of the insulating layer to form a spacer in the through hole and over the ferroelectric layer; and forming a top electrode over the ferroelectric layer and between the spacer.

Abstract: A non-transitory medium of a device that stores one or more instructions is provided. The instructions, when executed by a processing unit of the device, cause the device to: determine an affine enabled flag corresponding to one or more image frames from the bitstream; determine a maximum index corresponding to the one or more image frames from the bitstream when the affine enabled flag is true; determine that a maximum number of zero or more subblock-based merging motion vector prediction (MVP) candidates is in a number range of 1 to N and generated by subtracting the index value of the maximum index from N when the affine enabled flag is true and K is 1, N being a first integer and K being a second integer less than N; and reconstruct the one or more image frames based on the maximum number of zero or more subblock-based merging MVP candidates.

Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.

Abstract: An integrated circuit (IC) structure includes first and second active areas extending in a first direction in a semiconductor substrate, first and second gate structures extending in a second direction perpendicular to the first direction, wherein each of the first and second gate structures overlies each of the first and second active areas, a first metal-like defined (MD) segment extending in the second direction between the first and second gate structures and overlying each of the first and second active areas, and an isolation structure positioned between the first MD segment and the first active area. The first MD segment is electrically connected to the second active area and electrically isolated from a portion of the first active area between the first and second gate structures.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

Abstract: A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.

Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A method of decoding video data by an electronic device is provided. The method receives the video data, and determines, from an image frame, a block unit and a plurality of neighboring regions neighboring the block unit according to the video data. In addition, the method filters the plurality of neighboring regions neighboring the block unit to generate a plurality of template gradients. The method then derives a plurality of intra candidate modes based on the plurality of template gradients, and generates a plurality of template predictions, each of which being associated with one of the plurality of intra candidate modes. The method reconstructs the block unit based on the plurality of template predictions.

Abstract: The present invention relates to a nucleic acid amplification method and device, and a nucleic acid detection method and device. The nucleic acid amplification device comprises a reaction unit, an energy excitation unit, an operation unit, and an auxiliary cooling unit; the reaction unit comprises a target analyte to be detected, one or more solid-phase carriers, and a nucleic acid amplification reaction solution; each solid-phase carrier has a functionalized specific surface ligand to provide purification, separation, and nucleic acid amplification reaction of a target analyte to be detected; and energy output and an enabling/disabling time sequence of the energy excitation unit are controlled to generate a reaction temperature (thermal) cycle, so that an in-situ environment is formed around each solid-phase carrier during the cycle, and in-situ nucleic acid amplification reaction is performed in the in-situ environment to generate amplicons.

Abstract: A semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material.

Abstract: A semiconductor device includes a base isolation layer, a first transistor with a first source electrode at a first side of the base isolation layer. A bridge pillar extends through the base isolation layer, and a metal electrode electrically connects the bridge pillar to the first source electrode. The metal electrode and the first source electrode are at the same side of the base isolation layer. A second metal electrode at an opposite side of the base isolation layer electrically connects to the bridge pillar and to a conductive line at the second side of the base isolation layer.

Abstract: Disclosed herein, inter alia, are a crystalline compound of mAChR M1 antagonist, its pharmaceutical composition and methods of treatment.

Abstract: A broadside antenna includes a first radiation element and a second radiation element arranged at an interval, a first grounding element and a second grounding element arranged at an interval, and a first excitation element. A first gap is formed between the first radiation element and the second radiation element. The first excitation element includes a first feeding structure and a first extension stub that are arranged at an interval. The first feeding structure includes a first feed-in part connected to a feed source. The first extension stub is located on a side of the first feeding structure adjacent close to the first feed-in part. The first extension stub includes a first grounding part adjacent to the first feed-in part. The first grounding part is connected to the grounding surface.