Abstract: A method includes forming a first III-V compound layer over a substrate; forming a second III-V compound layer over the first III-V compound layer, wherein the first and second III-V compound layers include different materials; forming a first crystalline oxide layer over the second III-V compound layer; and forming a first crystalline interfacial layer over the first crystalline oxide layer.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a transistor device. The method may be performed by forming an anode and a cathode over an electron supply layer disposed on a semiconductor material. A doped III-N semiconductor material is formed over the electron supply layer, and an insulating material is formed over the electron supply layer and the doped III-N semiconductor material. The insulating material continuously extends from over the anode to over the cathode. The insulating material is patterned to form sidewalls of the insulating material that define an opening over the doped III-N semiconductor material. A gate structure is formed directly between the sidewalls of the insulating material and over the doped III-N semiconductor material.

Abstract: An embodiment of the invention shows a high-voltage MOS field-effect transistor connected in series with a Schottky diode. When the Schottky diode is forwardly biased, the high-voltage MOSFET can act as a switch and sustain a high drain-to-source voltage. When the Schottky diode is reversely biased, the Schottky diode can protect the integrate circuit where the high-voltage MOSFET is formed, because the integrate circuit might otherwise burn out due to an exceedingly-large reverse current.

Abstract: An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

Abstract: A method includes forming a first III-V compound layer over a substrate; forming a second III-V compound layer over the first III-V compound layer, wherein the first and second III-V compound layers include different materials; forming a first crystalline oxide layer over the second III-V compound layer; and forming a first crystalline interfacial layer over the first crystalline oxide layer.

Abstract: A vehicle headlamp structure free of reflective internal elements includes a lens and a light source. The lens includes a light emitting surface, a bottom surface, and a connecting surface. The light emitting surface is flat and the bottom surface includes at least one depression in the bottom surface to form at least one light incident structure. The at least one light incident structure includes a first light incident surface. The connecting surface is composed of a plurality of curved surfaces each with a different radius of curvature. The light source is substantially accommodated within the light incident structure and emits light through the first light incident surface to form an elliptical beam.

Abstract: A high-voltage startup circuit in an integrated circuit with a high-voltage pin and an operating voltage pin is disclosed, capable of having both low standby power consumption and high-speed transient response. An ultra-high voltage transistor and a main NMOS transistor are connected in series via a joint node between the high-voltage pin and the operating voltage pin. A pull-up circuit controlled by a stop signal is connected between the joint node and a first gate of the main NMOS transistor. A pull-down circuit controlled by the stop signal is connected to the first gate of the main NMOS transistor. When the stop signal is de-asserted the pull-up circuit couples the joint node to the first gate. When the stop signal is asserted the pull-up circuit performs an open circuit and the pull-down circuit pulls down the first gate voltage.

Abstract: A high-voltage startup circuit in an integrated circuit with a high-voltage pin and an operating voltage pin is disclosed, capable of having both low standby power consumption and high-speed transient response. An ultra-high voltage transistor and a main NMOS transistor are connected in series via a joint node between the high-voltage pin and the operating voltage pin. A pull-up circuit controlled by a stop signal is connected between the joint node and a first gate of the main NMOS transistor. A pull-down circuit controlled by the stop signal is connected to the first gate of the main NMOS transistor. When the stop signal is de-asserted the pull-up circuit couples the joint node to the first gate. When the stop signal is asserted the pull-up circuit performs an open circuit and the pull-down circuit pulls down the first gate voltage.

Abstract: A High Electron Mobility Transistor (HEMT) and a method of forming the same are disclosed. The HEMT includes a first III-V compound layer having a first band gap and a second III-V compound layer having a second band gap over the first III-V compound layer, wherein the second band gap is greater than the first band gap. The HEMT further includes a first oxide layer over the second III-V compound layer; a first interfacial layer over the first oxide layer; and a passivation layer over the first interfacial layer.

Abstract: A projection lens on a vehicle headlight includes a light incident surface and a light emitting surface facing away from the light incident surface. The light emitting surface includes a diffusing surface and a rough surface. A number of strips protrude from the diffusing surface. The strips are parallel to each other and have curved cross sections, and are configured for diffusing the light passing through the diffusing surface. The rough surface is positioned above and connected to the diffusing surface to form a horizontal connecting line, thereby allowing the rough surface to scatter the light passing through the rough surface in all directions.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer. Source and drain regions are arranged over the second III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: A cutter fastening assembly has a tool block, a fastening bolt, a fastening unit, a collet, and a cutter holder. The fastening bolt, the fastening unit, and the collet are mounted inside the tool block. The cutter holder has an assembling seat and a threaded hole. The assembling seat is integrally formed on the cutter holder and has a flange portion. The threaded hole is axially defined inside the flange portion and is screwed with the fastening bolt to keep the cutter holder connecting with the tool block.

Abstract: The present disclosure, in some embodiments relates to a semiconductor device. The semiconductor device includes a layer of semiconductor material disposed over a substrate and an electron supply layer disposed over the layer of semiconductor material between an anode terminal and a cathode terminal. A layer of III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer contacts an upper surface of the electron supply layer and further contacts an upper surface and a sidewall of the layer of III-N semiconductor material. A gate structure is separated from the layer of III-N semiconductor material by the passivation layer.

Abstract: An apparatus, computer program, and method are provided for setting a power of a cell node based on cell node gradient information. Cell node gradient information is generated based on a multiple-codeword channel quality indicator (CQI), utilizing a multiple-input-multiple-output (MIMO)-capable cell node in a network configured for communicating with a plurality of MIMO-capable user equipment. Additionally, other cell node gradient information is received that is generated for a plurality of other MIMO-capable cell nodes. The generated cell node gradient information and the other cell node gradient information are processed. Further, a power of the MIMO-capable cell node is set, based on the processing.

Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

Abstract: An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.