Patents by Inventor Chin Wu

Chin Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11841619
    Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMINCONDUTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsu-Ting Huang, Tung-Chin Wu, Shih-Hsiang Lo, Chih-Ming Lai, Jue-Chin Yu, Ru-Gun Liu, Chin-Hsiang Lin
  • Patent number: 11807903
    Abstract: The present disclosure provides methods and compositions for tracking nucleic acid fragment origin by target-specific barcode tagging when original nucleic acid targets break into small fragments. Nucleic acid targets are captured in vitro on a solid support with clonally localized nucleic acid barcode templates. Many nucleic acid targets canbe processed simultaneously in a massively parallel fashion without partition. These nucleic acid target tracking methods can be used for a variety of applications in both whole genome sequencing and targeted sequencing in order to accurately identify genomic variants, haplotype phasing and assembly, for example.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: November 7, 2023
    Assignee: Universal Sequencing Technology Corporation
    Inventors: Zhoutao Chen, Tsai-Chin Wu, Long Kim Pham, Yong Wang
  • Publication number: 20230345646
    Abstract: A display panel adapted to a spherical display device includes a substrate and a plurality of display configuration groups. The display configuration groups are arranged on the substrate along a first direction. Each of the display configuration groups corresponds to a display number and a display pitch. Each of the display configuration groups comprises at least one display row arranged along the first direction. Each of the at least one display row of each of the display configuration groups is arranged along a second direction orthogonal to the first direction according to the corresponding display number and the corresponding display pitch. The display configuration groups include a first configuration group and a second configuration group adjacent to each other, and the display pitch of the first configuration group is different from the display pitch of the second configuration group.
    Type: Application
    Filed: December 30, 2022
    Publication date: October 26, 2023
    Inventors: Yea-Ching CHEN, Chih-Kai WANG, Yu-Chin WU
  • Publication number: 20230341111
    Abstract: A light box structure includes a bracket and a board. The bracket is in an arc shape and has a first surface and a second surface opposite to each other. The board has a plurality of magnetic positioning posts. The magnetic positioning posts have at least two different heights. The board is attracted and attached on the first surface of the bracket through the magnetic positioning posts.
    Type: Application
    Filed: December 30, 2022
    Publication date: October 26, 2023
    Inventors: Li-Yuan LIAO, Chien-Hsin LIN, Ming-Chun HSU, Yu-Chin WU
  • Patent number: 11794447
    Abstract: A composite material structure includes a first fiber layer, a second fiber layer, and a third fiber layer. The first fiber layer is composed of a first long fiber and a first resin material. The second fiber layer is composed of a second long fiber and a second resin material. The third fiber layer is disposed between the first fiber layer and the second fiber layer. The third fiber layer is composed of a short fiber and a third resin material. A length of the first long fiber and a length of the second long fiber are both greater than a length of the short fiber, and the length of the short fiber is less than or equal to 25 mm.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: October 24, 2023
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Han-Ching Huang, Jung-Chin Wu, Kuo-Nan Ling, Sheng-Hung Lee
  • Patent number: 11769841
    Abstract: A method for fabricating a junction barrier Schottky diode device is disclosed. The junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: September 26, 2023
    Assignee: TAIPEI ANJET CORPORATION
    Inventors: Nobuo Machida, Wen-Tsung Chang, Wen-Chin Wu
  • Publication number: 20230174829
    Abstract: An optical adhesive film structure having an alignment function is provided. The optical adhesive film structure includes an optical adhesive layer and a release film. The release film is disposed on the optical adhesive layer. A first film surface of the release film facing away from the optical adhesive layer has a plurality of marks. The marks are recessed into the release film relative to the first film surface and do not run through the release film. A stitching display module and a manufacturing method of the stitching display module are also provided.
    Type: Application
    Filed: December 8, 2022
    Publication date: June 8, 2023
    Inventors: Yi-Hsin LIN, Wen-Lung CHEN, Yu-Chin WU, Wei-Lung LIAU
  • Publication number: 20230149533
    Abstract: The invention provides a SARS-CoV-2 mucosal vaccine composition, preparation, and use thereof. The SARS-CoV-2 mucosal vaccine composition comprises an antigen fusion protein which includes a SARS-CoV-2 antigen and a Type IIb heat-labile enterotoxin A subunit from Escherichia coli. Immunization with the antigen fusion protein elicits cellular and humoral immune responses, including systemic and mucosal immune responses, against SARS-CoV-2 in a subject, and thus protects the subject from viral infection.
    Type: Application
    Filed: August 5, 2022
    Publication date: May 18, 2023
    Inventors: SUH CHIN WU, PIN-HAN CHOU, HE-CHIN HSIEH
  • Patent number: 11646382
    Abstract: A junction barrier Schottky diode device and a method for fabricating the same is disclosed. In the junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: May 9, 2023
    Assignee: TAIPEI ANJET CORPORATION
    Inventors: Nobuo Machida, Wen-Tsung Chang, Wen-Chin Wu
  • Publication number: 20230120224
    Abstract: A prediction model training apparatus and method are provided. The apparatus classifies a plurality of data into a normal situation data set and a non-normal situation data set, wherein each of the data comprises a plurality of first features. The apparatus trains a first prediction model based on the normal situation data set and a plurality of third features among the first features. The apparatus inputs the non-normal situation data set to the first prediction model to generate a first stage prediction value. The apparatus adds the first stage prediction value to the non-normal situation data set. The apparatus trains a second prediction model based on the non-normal situation data set and the first features.
    Type: Application
    Filed: January 6, 2022
    Publication date: April 20, 2023
    Inventors: Chang En YANG, Ching Wen CHANG, Shu-Tzu HUANG, Chin-Wu LEE
  • Publication number: 20230110516
    Abstract: The present disclosure relates to immunogenic compositions comprising a severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) antigen, and a toll-like receptor 9 (TLR9) agonist, such as an oligonucleotide comprising an unmethylated cytidine-phospho-guanosine (CpG) motif. The immunogenic compositions are suitable for stimulating an immune response against a SARS-CoV-2 in an individual in need thereof.
    Type: Application
    Filed: March 1, 2021
    Publication date: April 13, 2023
    Applicants: Dynavax Technologies Corporation, MEDIGEN VACCINE BIOLOGICS CORPORATION
    Inventors: John D. CAMPBELL, Robert S. JANSSEN, David NOVACK, Tsun-Yung KUO, Charles CHEN, Chung-Chin WU, Yi-Jiun LIN, Meei-Yun LIN, Yu-Chi WU
  • Publication number: 20230070205
    Abstract: A network managing device for handling a data flow comprises a topology generating module, for generating a topology of at least one device of a network, and for determining at least one intelligent electric device (IED) of the at least one device according to the topology; a transmitting module, coupled to the topology generating module, for transmitting a request to a reception-transmission device, wherein the request is for requesting a substation information associated with the at least one IED; a receiving module, coupled to the transmitting module, for receiving the substation information from the reception-transmission device; a shortest path generating module, coupled to the receiving module, for generating a first shortest path of the at least one IED according to the substation information; and a data flow processing module, coupled to the shortest path generating module, for generating a data flow according to the first shortest path.
    Type: Application
    Filed: October 15, 2021
    Publication date: March 9, 2023
    Applicant: Moxa Inc.
    Inventors: Zhi-Jie Yang, Hsi-Chin Wu, Yu-Tzu Chang, Chuan Huang
  • Publication number: 20230058789
    Abstract: The present invention provides a SARS-CoV-2 chimeric VLP vaccine composition and an expressing vector and use thereof. The chimeric SARS-CoV-2 VLP comprises a VLP skeleton formed by the M1 protein and the M2 protein of influenza virus, and the chimeric spike protein of SARS-CoV-2, expressed on the surface of the VLP skeleton, the transmembrane domain of which is replaced by the transmembrane domain of a HA of influenza virus. The present invention also provides a recombinant vector expressing the chimeric SARS-CoV-2 VLP, and the use of the chimeric SARS-CoV-2 VLP for eliciting an immune response against SARS-CoV-2 variants.
    Type: Application
    Filed: August 1, 2022
    Publication date: February 23, 2023
    Inventors: SUH CHIN WU, Wei Shuo Lin, Ting Hsuan Chen
  • Publication number: 20230049405
    Abstract: A method includes patterning a hard mask over a target layer, capturing a low resolution image of the hard mask, and enhancing the low resolution image of the hard mask with a first machine learning model to produce an enhanced image of the hard mask. The method further includes analyzing the enhanced image of the hard mask with a second machine learning model to determine whether the target layer has defects.
    Type: Application
    Filed: February 11, 2022
    Publication date: February 16, 2023
    Inventors: Chih-Kai Yang, Tung-Chin Wu, Yu-Tien Shen, Hsiang Ming Chang, Chun-Yen Chang, Ya Hui Chang, Zengqin Zhao
  • Patent number: 11567810
    Abstract: Migrating workloads between a plurality of execution environments, including: identifying, in dependence upon on characteristics of a workload, one or more execution environments that can support the workload; determining, for each execution environment, costs associated with supporting the workload on the execution environment; selecting, in dependence upon the costs associated with supporting the workload on each the execution environments, a target execution environment for supporting the workload; and executing the workload on the target execution environment.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: January 31, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Chadd Kenney, Farhan Abrol, Lei Zhou, Yi-Chin Wu, Apoorva Bansal
  • Publication number: 20230021015
    Abstract: A method for fabricating a junction barrier Schottky diode device is disclosed. The junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 19, 2023
    Inventors: Nobuo MACHIDA, Wen-Tsung CHANG, Wen-Chin Wu
  • Patent number: 11552230
    Abstract: A pixel array substrate includes a base, pixel structures, first bonding pads, first wirings, and a first testing element. The pixel structures are disposed on an active area of a first surface of the base. The first bonding pads are disposed on a peripheral region of the first surface. Each of the first wirings is disposed on a corresponding first bonding pad, a first sidewall of the base, and a corresponding second bonding pad. The first testing element is disposed on the active area of the first surface and has a first testing line. The first testing line is electrically connected to at least one of the first bonding pads, and an end of the first testing line is substantially aligned with an edge of the base.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 10, 2023
    Assignee: Au Optronics Corporation
    Inventors: Shang-Jie Wu, Hao-An Chuang, Yu-Chieh Kuo, He-Yi Cheng, Che-Chia Chang, Yi-Jung Chen, Yi-Fan Chen, Yu-Hsun Chiu, Mei-Yi Li, Yu-Chin Wu
  • Publication number: 20230005795
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.
    Type: Application
    Filed: August 3, 2021
    Publication date: January 5, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Po-Ching Su, Yu-Fu Wang, Min-Hua Tsai, Ti-Bin Chen, Chih-Chiang Wu, Tzu-Chin Wu
  • Patent number: D984244
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: April 25, 2023
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventors: Yu-Chin Wu, Hsien-Chen Hu
  • Patent number: D993748
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: August 1, 2023
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventors: Yu-Chin Wu, Hsien-Chen Hu