Patents by Inventor Chin Wu

Chin Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10501529
    Abstract: Provided herein are a mutant envelope protein of Zika virus and a nucleic acid molecule including a nucleotide sequence encoding the mutant envelope protein. The mutant envelope protein, which preferably has a threonine substitution at 105th position, or an asparagine substitution at 248th position and a threonine substitution at 250th position in an amino acid sequence of SEQ ID NO: 1, includes an N-glycan masking a fusion loop region of the mutant envelope protein of Zika virus. Also provided herein is a vaccine composition, including the mutant envelope protein or a recombinant virus including the nucleic acid molecule. Also provided herein is a method of preventing Zika virus infection and reducing antibody-dependent enhancement of dengue virus infection, including administering to a subject in need thereof an effective amount of a vaccine composition including the mutant envelope protein of Zika virus.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 10, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Suh-Chin Wu, Shao-Ping Yang, Hsiao-Han Lin
  • Patent number: 10483334
    Abstract: A display panel comprising a first substrate, a second substrate, a color conversion layer, and an image sensing layer. A plurality of display units are between the first substrate and the second substrate. At least one of the plurality of display units has at least three sub-pixels. Each of the sub-pixels at least has one display region and a light shielding region disposed on at least one side of the display region. The color conversion layer is disposed in the display unit. Each of the color conversion elements is disposed in at least one portion of the light shielding region of each of the sub-pixels. The image sensing layer is disposed on the display unit and at least partially overlaps the color conversion layer. Each of the image sensing elements is disposed in at least one portion of the light shielding region of each of the sub-pixels to serve as an image sensing region.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: November 19, 2019
    Assignee: Au Optronics Corporation
    Inventors: Yu-Chin Wu, Chia-Tien Chou
  • Publication number: 20190348480
    Abstract: A display panel comprising a first substrate, a second substrate, a color conversion layer, and an image sensing layer. A plurality of display units are between the first substrate and the second substrate. At least one of the plurality of display units has at least three sub-pixels. Each of the sub-pixels at least has one display region and a light shielding region disposed on at least one side of the display region. The color conversion layer is disposed in the display unit. Each of the color conversion elements is disposed in at least one portion of the light shielding region of each of the sub-pixels. The image sensing layer is disposed on the display unit and at least partially overlaps the color conversion layer. Each of the image sensing elements is disposed in at least one portion of the light shielding region of each of the sub-pixels to serve as an image sensing region.
    Type: Application
    Filed: July 18, 2018
    Publication date: November 14, 2019
    Applicant: Au Optronics Corporation
    Inventors: Yu-Chin Wu, Chia-Tien Chou
  • Patent number: 10468417
    Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: November 5, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
  • Patent number: 10445551
    Abstract: A fingerprint identification device and a method for manufacturing the fingerprint identification device are provided. The fingerprint identification device includes a solder ball array, a re-distribution layer, an image sensing integrated circuit (IC), a light emitting circuit, a photic layer and a molding material. The re-distribution layer disposed on the solder ball array is electrically connected to a plurality of solder balls. The image sensing IC includes a plurality of through silicon vias (TSVs), and the TSVs are correspondingly electrically connected to the solder balls, respectively, through the re-distribution layer. The light emitting circuit is disposed on one side of the image sensing IC, and electrically connected to the image sensing IC through the re-distribution layer. The image sensing IC controls the light emitting circuit. The photic layer is disposed on the image sensing IC. The molding material encloses the image sensing IC.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: October 15, 2019
    Assignee: EOSMEM CORPORATION
    Inventors: Chern-Lin Chen, Shuang-Chin Wu, Ying-Yi Wu
  • Patent number: 10446559
    Abstract: A method of fabricating a DRAM includes providing a substrate. Later, a first mask layer is formed to cover the substrate. The first mask layer includes a hydrogen-containing silicon nitride layer and a silicon oxide layer. The hydrogen-containing silicon nitride layer has the chemical formula: SixNyHz, wherein x is between 4 and 8, y is between 3.5 and 9.5, and z equals 1. After that, the first mask layer is patterned to form a first patterned mask layer. Next, the substrate is etched by taking the first patterned mask layer as a mask to form a word line trench. Subsequently, the first patterned mask layer is removed entirely. Finally, a word line is formed in the word line trench.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: October 15, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Chao-An Liu, Ching-Hsiang Chang, Yi-Wei Chen
  • Publication number: 20190287976
    Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
    Type: Application
    Filed: April 23, 2018
    Publication date: September 19, 2019
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
  • Publication number: 20190248875
    Abstract: Provided herein are a mutant envelope protein of Zika virus and a nucleic acid molecule including a nucleotide sequence encoding the mutant envelope protein. The mutant envelope protein, which preferably has a threonine substitution at 105th position, or an asparagine substitution at 248th position and a threonine substitution at 250th position in an amino acid sequence of SEQ ID NO: 1, includes an N-glycan masking a fusion loop region of the mutant envelope protein of Zika virus. Also provided herein is a vaccine composition, including the mutant envelope protein or a recombinant virus including the nucleic acid molecule. Also provided herein is a method of preventing Zika virus infection and reducing antibody-dependent enhancement of dengue virus infection, including administering to a subject in need thereof an effective amount of a vaccine composition including the mutant envelope protein of Zika virus.
    Type: Application
    Filed: July 17, 2018
    Publication date: August 15, 2019
    Inventors: Suh-Chin Wu, Shao-Ping Yang, Hsiao-Han Lin
  • Publication number: 20190254178
    Abstract: A display device and a manufacturing method thereof are provided. The manufacturing method of the display device includes following steps: assembling a protection substrate and a display panel, wherein the protection substrate has an inner surface, facing a first surface of the display panel, and an end portion extends towards the display panel; assembling a device component and the display panel disposed between the device component and the protection substrate, wherein the device component has a component side surface, the display panel has a side surface, and a gap is formed among the end portion, the component side surface and the side surface; extending a dispensing extending portion to the gap; and dispensing an adhesive to the side surface and the component side surface to form an adhesive layer.
    Type: Application
    Filed: January 21, 2019
    Publication date: August 15, 2019
    Inventors: Chien-Wei CHEN, Tung-Chin WU, Ting-Hsuan LIN, Chih-Chiao YANG
  • Publication number: 20190225979
    Abstract: Provided is an influenza mucosal vaccine composition and preparation and application thereof. This composition contains an antigen fusion protein which includes an influenza virus antigen and a Type IIb heat-labile enterotoxin A subunit from Escherichia coli. Immunization with this antigen fusion protein induces cellular and humoral immune responses, including systemic and mucosal immune responses, against a specific influenza virus in a subject, and therefore protects the subject from viral infection.
    Type: Application
    Filed: August 3, 2018
    Publication date: July 25, 2019
    Inventors: Suh-Chin Wu, Shi-Wei Lin, Neos Tang, Ting-Hsung Chen
  • Publication number: 20190221570
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.
    Type: Application
    Filed: February 14, 2018
    Publication date: July 18, 2019
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Tzu-Chin Wu, Wei-Lun Hsu
  • Publication number: 20190207913
    Abstract: A data encryption and decryption method is provided. The method is used in a data encryption and decryption system and includes: establishing, by a data encryption and decryption device, a first secure sockets layer (SSL) connection with a mobile device; receiving a data transmitted from the mobile device; generating a first symmetric key, encrypting the data using the first symmetric key, and generating first encrypted data; encrypting the first symmetric key using a first public key, and generating a first encrypted key; and transmitting the first encrypted data and the first encrypted key to the mobile device.
    Type: Application
    Filed: August 31, 2016
    Publication date: July 4, 2019
    Inventors: Gwan-Hwan HWANG, Shih-Wei WANG, Tsu-Chin WU
  • Publication number: 20190206982
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Patent number: 10332888
    Abstract: A method of manufacturing memory devices is provided in the present invention. The method includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer and an upper electrode layer and a top plate, forming a tungsten layer on the upper electrode, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a pre-metal dielectric layer on the tungsten nitride layer.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 25, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Han-Yung Tsai, Tzu-Chin Wu
  • Patent number: 10320641
    Abstract: The present disclosure illustrates a switch device for substation and an error warning method thereof. The switch device accesses and copies a generic object oriented substation event (GOOSE) packet, and when the copied GOOSE packet is determined to trigger an abnormal condition event, the switch device generates and transmits an abnormal condition event confirmation request to an upstream switch device. A warning message is issued when a ready response cannot be received by the switch device from the upstream switch device. Therefore, the technical effect of quickly and accurately finding the switch device triggering the abnormal condition event first to facilitate repair may be achieved.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: June 11, 2019
    Assignee: MOXA INC.
    Inventor: Hsi-Chin Wu
  • Patent number: 10312080
    Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 4, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Mei-Ling Chen, Wei-Hsin Liu, Yi-Wei Chen, Ching-Hsiang Chang, Jui-Min Lee, Chia-Lung Chang, Tzu-Chin Wu, Shih-Fang Tzou
  • Publication number: 20190148382
    Abstract: A method of manufacturing memory devices is provided in the present invention. The method includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer and an upper electrode layer and a top plate, forming a tungsten layer on the upper electrode, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a pre-metal dielectric layer on the tungsten nitride layer.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Han-Yung Tsai, Tzu-Chin Wu
  • Patent number: 10288791
    Abstract: An expansion card with homogenized light outputs and light-homogenizing device thereof are disclosed. The expansion card includes a circuit board and a light-homogenizing device. The circuit board includes a light-emitting device disposed on a first side edge. The light-homogenizing device includes a light-guiding body, a light-diffusion element, and a light-turning element. The light-guiding body includes a light-input side and a light-output side opposite to each other, and the light-input side is adjacent to the first side edge. The light-diffusion element is disposed on the light-input side of the light-guiding body and opposite to the light-emitting device. The light-diffusion element and the light-out side are configured to diffuse the light beams entering into the light-guiding body from the light-emitting device and form a light-transmitting path.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 14, 2019
    Assignee: APACER TECHNOLOGY INC.
    Inventors: Hua-Min Tseng, Ming-Han Chung, Wen-Chin Wu, Chien-Pang Chen
  • Patent number: 10276650
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Patent number: 10262895
    Abstract: The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: April 16, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Mei-Ling Chen, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Ching-Hsiang Chang, Tzu-Chin Wu, Shih-Fang Tzou