Abstract: A display device is disclosed, which includes: a substrate having a first edge, wherein the first edge is parallel to a first direction, and the substrate has a display region and a border region adjacent to the display region; a first insulating layer disposed on the substrate; a first electrode layer disposed on the first insulating layer; and a second insulting layer disposed on the first electrode layer, wherein the second insulating layer comprises plural protrusions, the protrusions are disposed in the border region, and the protrusions are arranged along the first direction.

Abstract: A display device includes: a substrate; a thin film transistor structure disposed on the substrate and including a gate electrode and a drain electrode; and a data line disposed on the substrate. Herein, from a top view, the data line is separated from the drain electrode, an edge of the gate electrode overlaps the drain electrode, the edge has two ends, and a first direction is parallel to a connection line of the two ends. In addition, from the top view, the drain electrode has a first distance and a second distance, the first distance is a maximum distance of the drain electrode not overlapping the gate electrode in the first direction, the second distance is a maximum distance of the drain electrode overlapping the gate electrode in the first direction, and the first distance is greater than the second distance.

Abstract: A display panel is disclosed, which includes: a substrate; a scan line disposed on the substrate and extending along a first direction, wherein a first reference line parallel to the first direction and locating on the scan line is defined; data lines disposed on the substrate and extending along a second direction different from the first direction; an insulating layer disposed on the substrate and having an opening; and a shielding pattern disposed between two adjacent data lines and overlapping the scan line, wherein the shielding pattern includes first and second regions, the first region overlaps the opening and has a first outer edge, and the second region is adjacent to the first region and has a second outer edge. A first distance between the first outer edge and the first reference line is greater than a second distance between the second outer edge and the second reference line.

Abstract: A display panel includes a first scan line and a second scan line adjacent to the first scan line disposed on the first substrate. A common electrode line is adjacent to the first scan line or the second scan line. The common electrode line has an enlarged portion, and an extending direction of the common electrode line is substantially the same as an extending direction of the first scan line. A first data line and a second data line adjacent to the first data line are disposed on the first substrate. In a direction perpendicular to the extending direction of the common electrode line, the enlarged portion has a maximum width, a part of the common electrode line overlapping the first data line has a maximum width, and the maximum width of the enlarged portion is greater than the maximum width of the first data line.

Abstract: A button structure includes a button and a fixing portion; wherein the fixing portion is configured for fixing the button, the fixing portion includes a first latching portion and a second latching portion, and the first latching portion includes a first latching opening, and the second latching portion includes a second latching opening, and the first latching opening has an opening direction substantially perpendicular to an opening direction of the second latching opening, and the first latching opening and the second latching opening are engaged with the button. An electronic device is also provided. The electronic device includes a housing and the button structure, the button structure is received in the housing.

Abstract: A display device is disclosed, which includes: a support layer including a first surface, a second surface and a first side wall, wherein the first surface and the second surface locate at two opposite sides of the support layer, and the first side wall connects the first surface and the second surface; an adhesion layer disposed on the second surface of the support layer; a base layer disposed on the adhesion layer; and at least one transistor disposed on the base layer, wherein the adhesion layer adheres to a partial portion of the first side wall of the support layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin structure, and a second fin structure. The method includes forming a gate structure over the first fin structure and the second fin structure. The method includes forming a first source structure and a first drain structure on the first fin structure and on two opposite sides of the gate structure. The first source structure and the first drain structure are made of an N-type conductivity material. The method includes forming a cap layer over the first source structure and the first drain structure. The cap layer is doped with a Group IIIA element, and the cap layer adjacent to a top surface of the first source structure is thicker than the cap layer adjacent to a bottom surface of the first source structure.

Abstract: A display substrate is provided. The display substrate includes a first insulating layer disposed on a substrate, a second insulating layer disposed on the first insulating layer. In particular, the first insulating layer has a first opening and the second insulating layer has a second opening, wherein the first opening and the second opening are partially overlapped. Further, in a cross-sectional view, the first insulating layer corresponding to the first opening has two first bottom ends, and the second insulating layer corresponding to the second opening has two second bottom ends, a location of a first vertical central line between the two first bottom ends is different from a location of a second vertical central line between the two second bottom ends, and the first vertical central line and the second vertical central line are substantially parallel to a normal direction of the surface.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first device region and a second device region, a first fin over the substrate in the first device region, a second fin over the substrate in the second device region, a first epitaxial feature over the first fin in the source/drain region of the first fin, a second epitaxial feature over the second fin in the source/drain region of the second fin, and a dielectric layer on the first and second epitaxial features. The first epitaxial feature is doped with a first dopant of a first conductivity and the second epitaxial feature is doped with a second dopant of a second conductivity different from the first conductivity. The dielectric layer is doped with the first dopant.

Abstract: A display device is disclosed, which includes: a substrate; a first metal conductive layer disposed on the substrate; a semiconductor layer disposed on the first metal conductive layer; and a second metal conductive layer disposed on the semiconductor layer and including a data line, a first part and a second part separated from the first part, the data line with a data extending direction connected to the second part. A first extending direction is a direction that the first part extends toward the second part, a first region is a region that the first part overlaps the first metal conductive layer, the first part has a first maximum breadth outside the first region along the data extending direction and a second maximum breadth inside the first region along a direction substantially perpendicular to the first extending direction, and the first maximum breadth is greater than the second maximum breadth.

Abstract: The present disclosure relates to anti-SSEA4 antibodies and bindings fragments thereof comprising specific complementarity determining regions capable of high affinity binding to SSEA4 molecules and SSEA4-associated expressing tumor cells, such as breast cancer, pancreatic cancer, and renal cancer cells. The anti-SSEA4 antibodies and binding fragments induce ADCC or CDC effects in the targeted tumor cells and inhibit and/or reduce the cancer/tumor proliferation. The present disclosure also provides anti-SSEA4 antibodies and binding fragments thereof as a pharmaceutical composition for treating cancer. In addition, the anti-SSEA4 antibodies and binding fragments are useful in the diagnosis of cancers.

Abstract: In an embodiment, a method includes: forming a first gate stack and a second gate stack on a fin; etching the fin to form a recess in the fin between the first gate stack and the second gate stack; forming an epitaxial source/drain region in the recess, the forming including: forming a first layer lining sides and a bottom of the recess by dispensing silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess; and after forming the first layer, forming a second layer on the first layer by dispensing the silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess, where each of the silane, dichlorosilane, trichlorosilane, and hydrochloric acid are dispensed at a first flow rate when forming the first layer and at a second flow rate when forming the second layer.

Abstract: A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin adjacent to the gate structure; and forming a source/drain region in the recess, the source/drain region including a first layer, a second layer, and a third layer, where forming the source/drain region includes performing a first epitaxy process under first process conditions to form the first layer in the recess, the first layer extending along surfaces of the fin exposed by the recess; performing a second epitaxy process under second process conditions to form the second layer over the first layer; and performing a third epitaxy process under third process conditions to form the third layer over the second layer, the third layer filling the recess, where the first processing conditions, the second process conditions and the third process conditions are different.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: A display apparatus including a substrate, a gate line, first and second driving transistors, and a color filter layer is provided. The substrate has first and second light emitting regions and a circuit region. The first light emitting region is disposed to be adjacent to the second light emitting region, and the circuit region is disposed to be adjacent to the first and second light emitting regions. The gate line is disposed in the circuit region and extends along a direction. The first and second driving transistors are respectively disposed in the circuit region, have a channel region, and corresponds to the first and second light emitting regions. The color filter layer has a main portion in the first light emitting region and an extending portion in the circuit region and connected to the main portion. The extending portion extends along the direction and overlaps the channel regions.

Abstract: The present invention is related to an active substance of Hericium erinaceus having a pain-relieving effect, and a pharmaceutical composition including the active substance. The active substance is prepared using the following steps: (a) inoculating a mycelium of H. erinaceus on an agar plate and incubating at 15-32° C. for 8-16 days; (b) inoculating the incubated H. erinaceus mycelia from step (a) into a medium in a flask and incubating at 20-30° C. and pH 4.5-6.5 for 3-5 days; (c) inoculating the incubated H. erinaceus mycelia from step (b) into a medium in a fermentation tank and incubating at 24-32° C. and pH 4.5-5.5 for 8-16 days to obtain a fermented medium of the H. erinaceus mycelia; and (d) desiccating the fermented medium of the H. erinaceus mycelia from step (c) to obtain the powder of the H. erinaceus mycelia, which is further purified and isolated to obtain a novel compound of H. erinaceus.

Abstract: A camera module includes multiple camera units, a bracket, and multiple mounting rods. Each of the camera units includes a main body and a lens on the main body. The main body includes two protrusions. The two protrusions protrude from opposite sides of the main body. Each of the two protrusions includes a fixing hole. The bracket is mounted in an electronic device and includes multiple mounting holes and multiple mounting grooves disposing in a surface of the bracket. Each two of the multiple mounting grooves connect with corresponding mounting holes at opposite sides of the mounting holes. The mounting rods protrude from the mounting grooves. When the mounting holes receive the camera units, the corresponding mounting grooves receive the corresponding protrusions and the mounting rods pass through the corresponding fixing holes.

Abstract: A display panel and a display device applying the same are provided. The display panel includes a first substrate, a second substrate, and a display medium disposed between the first substrate and the second substrate. The first substrate includes a first conductive layer having a first line width and a second conductive layer having a second line width smaller than the first line width. A first spacing is defined by a first sidewall of the second conductive layer and a second sidewall, located on the same side as the first sidewall, of the first conductive layer. A second spacing is defined by a third sidewall of the second conductive layer opposite to the first sidewall and a fourth sidewall, located on the same side as the third sidewall, of the first conductive layer. The first spacing is greater than the second spacing.

Abstract: A display panel including a first substrate having a pixel region, a thin film transistor, an insulating layer, a pixel electrode, a second substrate, and a display medium is provided. The thin film transistor is located on the first substrate and in the pixel region. The insulating layer is located in the pixel region and covers the thin film transistor. The insulating layer has a contact hole having a first maximum distance extending along a first direction and a second maximum distance extending along a second direction. The first direction is different from the second direction. The second maximum distance is longer than the first maximum distance. The pixel electrode is electrically connected to the thin film transistor through the contact hole. The display medium is located between the first substrate and the second substrate.

Abstract: The present disclosure relates to anti-SSEA4 antibodies and bindings fragments thereof comprising specific complementarity determining regions capable of high affinity binding to SSEA4 molecules and SSEA4-associated expressing tumor cells, such as breast cancer, pancreatic cancer, and renal cancer cells. The anti-SSEA4 antibodies and binding fragments induce ADCC or CDC effects in the targeted tumor cells and inhibit and/or reduce the cancer/tumor proliferation. The present disclosure also provides anti-SSEA4 antibodies and binding fragments thereof as a pharmaceutical composition for treating cancer. In addition, the anti-SSEA4 antibodies and binding fragments are useful in the diagnosis of cancers.