Abstract: A solar cell structure includes a semiconductor substrate having a front side and a back side; a pyramid structure disposed on the front side of the semiconductor substrate; a anti-reflection layer disposed on the pyramid structure; a front electrode provided on the anti-reflection layer; a passivation layer provided on the back side of the semiconductor substrate; a dielectric layer disposed on the passivation layer; and a back electrode disposed on the dielectric layer. The reflective layer is a multi-layer anti-reflection layer having at least three coating layers.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Abstract: The disclosed display device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; and a connecting member disposed on the substrate and electrically connecting to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, and a minimum width of the second part in a direction perpendicular to the extension direction is less than a maximum width of the first part in the direction.

Abstract: A method for bicycle fitting includes receiving evaluation factors based on one or more scenario parameters; positioning at least one of a saddle and a handlebar to one or more positions when a user is pedaling; determining values for the evaluation factors according to data received from one or more sensors at the one or more positions; and processing the values to identify one or more recommended positions for the saddle or the handlebar.

Abstract: This invention relates to an antimicrobial composition, especially one which provides synergistic anti-dandruff efficacy. This is achieved through a judicious combination of anti-dandruff agent zinc pyrithione and select antimicrobial lipids. These compositions can be delivered through shampoo or conditioner. Disclosed is an anti-microbial composition comprising: (i) 0.1 to 3% by weight of zinc pyrithione; (ii) 0.01 to 5.0% by weight of an antimicrobial lipid selected from sapienic acid, palmitoleic acid, sphingosine, dihydrosphingosine, and phytosphingosine; and a cosmetically acceptable vehicle, wherein said composition is a shampoo or a conditioner for preventing or alleviating the symptoms of dandruff on the scalp and/or hair and where an antimicrobial alcohol having 1 to 7 carbon atoms are absent from the composition.

Abstract: A method includes etching two source/drain regions over a substrate to form two source/drain trenches; epitaxially growing two source/drain features in the two source/drain trenches respectively; performing a cut process to the two source/drain features; and after the cut process, depositing a contact etch stop layer (CESL) over the two source/drain features.

Abstract: Methods and devices formed thereof that include a fin structure extending from a substrate and a gate structure is formed over the fin structure. An epitaxial feature is formed over the fin structure adjacent the gate structure. The epitaxial feature can include a hollow region (or dielectric filled hollow region) in the epitaxial source/drain region. A selective etching process is performed to remove at least a portion of an epitaxial region having a second dopant type to form the hollow area between the first epitaxial portion and the third epitaxial portion.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride (HF) and ammonia (NH3).

Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Abstract: The disclosed display device includes: a substrate; a gate electrode disposed on the substrate, wherein a first projection is defined by projecting the gate electrode on the substrate; and a connecting member disposed on the gate electrode and electrically connecting to the gate electrode, wherein a second projection is defined by projecting the connecting member on the substrate, an overlapping region is defined as a region of the second projection overlapping the first projection, and an area of the first projection is greater than an area of the overlapping region.

Abstract: A touch device is provided, including a first substrate and a circuit substrate. The first substrate includes a touch sensing structure and a plurality of first electrodes. The touch sensing structure is disposed on the first substrate. The first electrodes are arranged along a first direction. The first electrodes are disposed on the first substrate and electrically connected to the touch sensing structure, a first gap is formed between two adjacent first electrodes, and a minimum distance between the two adjacent first electrodes is a gap distance. The circuit substrate is partially overlapping the substrate in a vertical projection direction, the circuit substrate including a plurality of second electrodes corresponding to the first electrodes. One of the two adjacent first electrodes has a first electrode side edge facing the first gap. One of the second electrodes has a second electrode side edge located in the first gap.

Abstract: The present invention provides a housing having a housing shell with an opening, a guidance component and a door leaf set. The guidance component is arranged in the housing shell and extending along the direction away from the opening. The door leaf set has a first door leaf and a second door leaf. The first door leaf is pivotally connected the housing shell to enable the first door leaf to rotate to a first position or a second position relative to the opening. Wherein when the first door leaf is positioned at the first position, the first door leaf shields a portion of the opening; when the first door leaf is positioned at the second position, the first door leaf extends into the housing shell and defines the first installation space with the guiding component.

Abstract: A pixel circuit including a compensation circuit, a writing circuit, a light emitting element, and a power supplying circuit is provided. The compensation circuit comprises a first node, and provides a driving current to the light emitting element according to a voltage of the first node and a system high voltage. The writing circuit provides a data voltage to the compensation circuit according to a first control signal so that the compensation circuit sets the voltage of the first node. The power supplying circuit selectively couples the compensation circuit to the light emitting element, and provides the system high voltage and a system low voltage to the compensation circuit, in which the system low voltage is configured to reset the voltage of the first node. The first control signal and the second control signal are opposite to the first emission signal and the second emission signal, respectively.

Abstract: In an embodiment, a method includes: forming a first gate stack and a second gate stack on a fin; etching the fin to form a recess in the fin between the first gate stack and the second gate stack; forming an epitaxial source/drain region in the recess, the forming including: forming a first layer lining sides and a bottom of the recess by dispensing silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess; and after forming the first layer, forming a second layer on the first layer by dispensing the silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess, where each of the silane, dichlorosilane, trichlorosilane, and hydrochloric acid are dispensed at a first flow rate when forming the first layer and at a second flow rate when forming the second layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extended above a substrate, and a first source/drain structure formed over the first fin structure. The first source/drain structure is made of an N-type conductivity material. The semiconductor device structure also includes a second source/drain structure formed over the second fin structure, and the second source/drain structure is made of an P-type conductivity material The semiconductor device structure also includes a cap layer formed over the first source/drain structure, wherein the cap layer is made of P-type conductivity material.