Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a source/drain feature over a substrate, a plurality of semiconductor layers over the substrate, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a gate dielectric layer in contact with the gate electrode layer, and a cap layer. The cap layer has a first portion disposed between the plurality of semiconductor layers and the source/drain feature and a second portion extending outwardly from opposing ends of the first portion. The semiconductor device structure further includes a dielectric spacer disposed between and in contact with the source/drain feature and the second portion of the cap layer.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulaton process so as to form a plurality of semiconductor packages.

Abstract: A semiconductor device comprises a semiconductor substrate, a plurality of metal layers, an adhesive layer, a compound layer, and a plurality of contact pads. A thickness of the semiconductor substrate is in a range from 15 ?m to 35 ?m. A thickness of the compound layer is larger than the thickness of the semiconductor substrate. A coefficient of thermal expansion of the compound layer is less than or equal to 9 ppm/° C. A glass transition temperature of the compound layer is larger than 150° C. The plurality of metal layers comprises a first titanium layer, a first nickel layer, a silver layer, a second nickel layer, and a metallic layer. In a first example, the metallic layer is a second titanium layer. In a second example, the metallic layer is a Titanium Nitride (TiN) layer.

Abstract: A display apparatus includes a wireless transmission unit and a display panel. The display panel includes a substrate, a plurality of pixel units and a signal line. The substrate includes a display region and a periphery region. The periphery region surrounds the display region. The pixel units are disposed on the display region. Each of the pixel units includes an active device and a pixel electrode. The active device is electrically connected to the pixel electrode. The signal line is on the periphery region. As viewed from a top view, the signal line has an annular shape having a gap and surrounds the display region.

Abstract: A source separation method, an apparatus, and a non-transitory computer-readable medium are provided. Atrous Spatial Pyramid Pooling (ASPP) is used to reduce the number of parameters of a model and speed up computation. Conventional upsampling is replaced with a conversion between time and depth, and a receptive field preserving decoder is provided. In addition, temporal attention with dynamic convolution kernel is added, to further achieve lightweight and improve the effect of separation.

Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.

Abstract: A wafer level chip scale semiconductor package comprises a device semiconductor layer, a backside metallization layer, a film laminate layer, and a metal layer. The device semiconductor layer comprises a plurality of metal electrodes disposed on a front surface of the device semiconductor. Each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer. Each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer. A surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.

Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

Abstract: A method comprises the steps of providing a wafer; applying a redistribution layer, grinding a back side of the wafer; depositing a metal layer; and applying a singulation process. A semiconductor package comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a redistribution layer, and a metal layer. The MOSFET comprises a source electrode, a gate electrode, a drain electrode and a plurality of partial drain plugs. The source electrode, the gate electrode, and the drain electrode are positioned at a front side of the MOSFET.

Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.

Abstract: A display apparatus includes a wireless transmission unit and a display panel. The display panel includes a substrate, a plurality of pixel units and a signal line. The substrate includes a display region and a periphery region. The periphery region surrounds the display region. The pixel units are disposed on the display region. Each of the pixel units includes an active device and a pixel electrode. The active device is electrically connected to the pixel electrode. The signal line is on the periphery region. As viewed from a top view, the signal line has an annular shape having a gap and surrounds the display region.

Abstract: An electrical stimulation method is provided. The electrical stimulation method is applied to an electrical stimulation device and an external control device. The electrical stimulation method includes the following steps. The predetermined electrical stimulation level that corresponds to the predetermined target energy is obtained by the external control device. The predetermined target energy is one of the target energies in the first target energy set. The external control device selects the target energy upper bound and the target energy lower bound from the first target energy set according to the predetermined electrical stimulation level. The external control device generates a second target energy set according to the target energy upper bound and the target energy lower bound. The electrical stimulation device performs electrical stimulation of the target area of a target object according to the second target energy set.

Abstract: A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a semiconductor device structure is provided. The semiconductor device structure includes a substrate having a front side and a back side opposing the front side, a gate stack disposed on the front side of the substrate, and a first source/drain feature and a second source/drain feature disposed in opposing sides of the gate stack. Each first source/drain feature and second source/drain feature comprises a first side and a second side, and a portion of the back side of the substrate is exposed to an air gap.

Abstract: A display assistant device comprises a display, a camera, a speaker, microphones, a processor and memory. The memory stores programs comprising instructions that, when executed by the processor, enable a plurality of modes of the display assistant device. The modes include a monitoring mode and an assistant mode. In the monitoring mode, the device is configured to perform a remote monitoring function in which first video captured by the camera is streamed to a remote server system for monitoring uses. The monitoring uses include transmission of the first video to remote client devices authorized to access the first video. In the assistant mode, the device is configured to perform a second plurality of functions that excludes the monitoring function and includes a video communication function in which second video captured by the camera is transmitted to second devices participating in a video communication with a first user of the device.

Abstract: A machine learning method and a machine learning device are provided. The machine learning method includes: receiving an input signal and performing normalization on the input signal; transmitting the normalized input signal to a convolutional layer; and adding a sparse coding layer after the convolutional layer, wherein the sparse coding layer uses dictionary atoms to reconstruct signals on a projection of the normalized input signal passing through the convolutional layer, and the sparse coding layer receives a mini-batch input to refresh the dictionary atoms.

Abstract: An omnidirectional wheel includes a hub and a number of driven wheels. The hub defines a number of mounting grooves. Each mounting groove includes an axle provided therein. Each driven wheel includes a driven roller and a cover layer. Each of two ends of the driven roller defines a fixing hole. Each of the two holes receives the axle. The cover layer is sleeved on an outer side of the driven roller.

Abstract: Embodiments of the present disclosure includes a semiconductor device. The semiconductor device includes first suspended nanostructures vertically stacked over one another and disposed on a substrate, a first gate stack engaging the first suspended nanostructures, a first gate spacer disposed on sidewalls of the first gate stack, second suspended nanostructures vertically stacked over one another and disposed on the substrate, a second gate stack engaging the second suspended nanostructures, and a second gate spacer disposed on sidewalls of the second gate stack. A middle portion of the first suspended nanostructures has a first thickness measured in a direction perpendicular to a top surface of the substrate. A middle portion of the second suspended nanostructures has a second thickness measured in the direction. The second thickness is smaller than the first thickness.

Abstract: A structure for mounting a cooling fan easily and conveniently and in the correct orientation only includes a chassis and at least one fan module. The chassis has a block, a first nut, and a second nut. The fan module has at least one accessory. The block is mounted on the first nut or the second nut. When the block is fixed on the first nut, the fan module can only be placed and installed so as to blow air into the chassis, and when the block is fixed on the second nut, the fan module can only be installed so as to extract air out of the chassis, thereby ensuring the correct mode of operation. An electronic device and a server using the structure is also disclosed.

Abstract: The present disclosure provides a method for evaluating prognosis in a patient with breast cancer, including the following steps: (a) detecting the expression level of pyruvate kinase in a sample from the patient; (b) detecting the expression level of O-linked ?-N-acetylglucosamine in the sample; and (c) evaluating a clinical treatment score post-5 years, wherein high expression levels of both the pyruvate kinase and the O-GlcNAc, and high score of the CTS5 indicate that the patient has a poor prognosis. The present disclosure also provides a kit for evaluating prognosis in a patient with breast cancer.