Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: A method includes: obtaining impact values for characteristic conditions; selecting training data subsets respectively from training data sets according to the impact values; obtaining a candidate model and an evaluation value based on the training data subsets; supplementing the training data subsets according to the impact values; obtaining another candidate model and another evaluation value based on training data subsets thus supplemented; repeating the step of supplementing the training data subset, and the step of obtaining another candidate model and another evaluation value based on the training data subsets thus supplemented; and selecting one of the candidate models as a prediction model based on the evaluation values.

Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

Abstract: A circuit board structure is provided. The circuit board structure includes a via hole, a conductive layer, and an alternate stacking of a plurality of circuit layers and a plurality of insulating layers. The via hole penetrates through the plurality of circuit layers and the plurality of insulating layers. The lateral ends of the plurality of insulating layers form the sidewall of the via hole. The conductive layer is conformally disposed within the via hole. The conductive layer exposes the first region of the sidewall and covers the second region of the sidewall. The sidewall extends in the longitudinal direction of the via hole and has no misalignments in the radial direction.

Abstract: Methods and structures for modulating an inner spacer profile include providing a fin having an epitaxial layer stack including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. Thereafter, in some examples, the method includes conformally depositing a dielectric layer to substantially fill the first gap between the adjacent semiconductor channel layers. In some cases, the method further includes etching exposed lateral surfaces of the dielectric layer to form an etched-back dielectric layer that defines substantially V-shaped recesses. In some embodiments, the method further includes forming a substantially V-shaped inner spacer within the substantially V-shaped recesses.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.

Abstract: A semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a metal clip, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. The lead frame comprises one or more voltage input (Vin) leads; a gate lead; one or more switching node (Lx) leads; a first die paddle; a second die paddle; and an end paddle. Each of an exposed bottom surface of the one or more Lx leads is directly connected to an exposed bottom surface of the end paddle. A longitudinal direction of an exposed bottom surface of the gate lead is perpendicular to a longitudinal direction of each of the exposed bottom surface of the one or more Lx leads. An entirely of each of the one or more Vin leads is of the full thickness.

Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a nanostructure stack over the substrate. The method includes forming a gate stack over the nanostructure stack and the substrate. The method includes removing the first nanostructure forming a first gap between the substrate and the second nanostructure. The method includes forming a first spacer layer in the first gap and a gate spacer over a sidewall of the gate stack. The method includes partially removing the nanostructure stack, which is not covered by the gate stack and the gate spacer, to form a first trench in the nanostructure stack. The method includes forming a source/drain structure in the first trench and over the first spacer layer.

Abstract: A method for acquiring shadow-free images of a document for scanning or other purposes is applied in a device. The method includes training a shadow prediction model based on sample documents of a sample library and inputting a background color and a shadow mask of each of the sample documents extracted by the shadow prediction model into a predetermined shadow removing network for training, to obtain a shadow removing model. The method further includes obtaining a background color and a shadow mask of the document through the shadow prediction model and removing the shadows of the document based on the shadow removing model. The device utilizing the method is also disclosed.

Abstract: A semiconductor package includes a lead frame, a chip, and a molding encapsulation. The lead frame comprises a die paddle, a first plurality of leads, additional one or more leads, a second plurality of leads, a first tie bar, a second tie bar, a third tie bar, and a fourth tie bar. A respective end surface of each lead of the first plurality of leads, the additional one or more leads, and the second plurality of leads is plated with a metal. A respective end surface of the first tie bar, the second tie bar, the third tie bar, and the fourth tie bar is not plated with the metal. A method for fabricating a semiconductor package includes the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, applying a trimming process, applying a plating process, and applying a singulation process.

Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

Abstract: Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first and second semiconductor layers are alternately stacked over a substrate, is formed, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers are laterally etched in the source/drain space, a first insulating layer is formed on a sidewall of the source/drain space, the first insulating layer is partially etched, thereby forming a first bottom spacer at a bottom of the source/drain space, a second insulating layer is formed on the sidewall of the source/drain space, the second insulating layer is partially etched, thereby forming inner spacers on end faces of the first semiconductor layers and leaving a part of the second insulating layer as a second bottom spacer at the bottom of the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space.

Abstract: A circuit driving substrate, display panel and a display driving method are provided. The circuit driving substrate includes a pixel array, a first switching circuit, a second switching circuit, a first driving circuit and a second driving circuit. The first switching circuit is coupled to the pixel array through a plurality of gate lines, and receives a first switching signal. The second switching circuit is coupled to the pixel array through the gate lines, and receives a second switching signal. The first driving circuit is coupled to the first switching circuit and configured to output the first voltage signal to the first switching circuit. The second driving circuit is coupled to the second switching circuit and configured to output a second voltage signal to the second switching circuit. The first switching circuit and the second switching circuit selectively provide the first voltage signal or the second voltage signal.

Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.

Abstract: The present disclosure describes a semiconductor device having an asymmetric source/drain (S/D) design. The semiconductor device includes multiple semiconductor layers on a substrate, a gate structure wrapped around the multiple semiconductor layers, an inner spacer structure between the multiple semiconductor layers and in contact with a first side of the gate structure, and an epitaxial layer in contact with a second side of the gate structure. The second side is opposite to the first side.

Abstract: A display device includes a display region and a periphery region surrounding the display region. The display device includes an driving circuit substrate, a TFT array substrate, a front plane laminate, and multiple conductive wires. The driving circuit substrate includes multiple first conductive pads. The TFT array substrate includes multiple second conductive pads. The TFT array substrate is located on the driving circuit substrate. The TFT array substrate is located between the driving circuit substrate and the front plane laminate. The conductive wires are electrically connected with the first conductive pads and the second conductive pads, respectively. The first conductive pads and the second conductive pads are located in the periphery region.