Patents by Inventor Ching Wang

Ching Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IMMUNOSTIMULATORY LIPOPLEX, PHARMACEUTICAL COMPOSITION INCLUDING IMMUNOSTIMULATORY LIPOPLEX, AND USES THEREOF
    Publication number: 20220202952
    Abstract: An immunostimulatory lipoplex is provided. The immunostimulatory lipoplex includes a liposome and at least one immunostimulatory nucleic acid drug, and the immunostimulatory nucleic acid drug is complexed with the liposome The liposome includes 40 to 85 mol % of cationic lipid, 10 to 50 mol % of cholesterol, and 0.001 to 20 mol % of modified polyethylene glycol lipid.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 30, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Neng-Chang YU, Felice CHENG, Chih-Peng LIU, Ming-Hsi WU, Shih-Ta CHEN, Chia-Mu TU, Li-Wen CHANG, Jheng-Sian LI, Meng-Ping SHE, Hsiang-Ching WANG
  • METHOD FOR SEMI-WAFER LEVEL PACKAGING
    Publication number: 20220208724
    Abstract: A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Bo Chen
  • SEMICONDUCTOR PACKAGE HAVING WETTABLE LEAD FLANK AND METHOD OF MAKING THE SAME
    Publication number: 20220199425
    Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles, a first plurality of leads, and a second plurality of leads. A respective end surface of each lead of the first plurality of leads and the second plurality of leads is plated with a metal. A first respective window on a first side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A second respective window on a second side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A method for fabricating a semiconductor package comprises the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, and applying a cutting process or a punching process.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Long-Ching Wang, Lei Fukuda, Adrian Chee Heong Koh, Peter Wilson, Feng Ye
  • SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOF
    Publication number: 20220165842
    Abstract: Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 26, 2022
    Inventors: Chih-Ching Wang, Wen-Hsing Hsieh, Jon-Hsu HO, Wen-Yuan Chen, Chia-Ying Su, Chung-Wei WU, Zhiqiang Wu
  • Power semiconductor package having integrated inductor, resistor and capacitor
    Patent number: 11309233
    Abstract: A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: April 19, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventors: Xiaotian Zhang, Mary Jane R. Alin, Bo Chen, David Brian Oraboni, Jr., Long-Ching Wang, Jian Yin
  • Dielectric Fin Structure
    Publication number: 20220115530
    Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.
    Type: Application
    Filed: October 13, 2020
    Publication date: April 14, 2022
    Inventors: Yu-Shan Lu, Chung-I Yang, Kuo-Yi Chao, Wen-Hsing Hsieh, Jiun-Ming Kuo, Chih-Ching Wang, Yuan-Ching Peng
  • Method of fabricating semiconductor device including dummy via anchored to dummy metal layer
    Patent number: 11302654
    Abstract: A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • NUCLEIC ACID DETECTOR AND IMAGE-BASED NUCLEIC ACID DETECTION METHOD
    Publication number: 20220099623
    Abstract: An image-based nucleic acid detection method applied to a nucleic acid detector is provided. The method includes obtaining a plurality of images when detection liquid is performing electrophoresis. Once a target image is recognized from the plurality of images, a nucleic acid detection result is analyzed based on the target image.
    Type: Application
    Filed: August 13, 2021
    Publication date: March 31, 2022
    Inventors: KUAN-HUA WANG, YU-CHING WANG, YI-JEN HUANG, EN-CHIEH CHANG, CHUN-HSIANG HUANG, SHENG-CHIEN HUANG
  • VOICE CALLING WITH A CONNECTED DEVICE
    Publication number: 20220094720
    Abstract: Systems and techniques are provided for voice calling with a connected device that does not include a SIM card or telephone port. Outgoing audio data may be received at an embedded browser running on a connected device, may be sent using Web Real Time Communications (WebRTC) from the embedded browser to an integration layer running within the embedded browser, and may be sent from the integration layer to a border controller for a voice call carrier over a Session Initiation Protocol (SIP) connection according to Secure Real Time Transport Protocol (SRTP). Incoming audio data may be received at the integration layer from the border controller for the voice call carrier over the SIP connection according to SRTP, may be sent using WebRTC from the integration layer to the embedded browser, and may be sent from the embedded browser to an audio output of the connected device which may output audio.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 24, 2022
    Inventors: Jeffrey Ching Wang, Chien-Jung Kung, Madhusudhan R. Adupala
  • SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOF
    Publication number: 20220093743
    Abstract: Embodiments of the present disclosure provide semiconductor device structures having at least one T-shaped stacked nanosheet transistor to provide increased effective conductive area across the channel regions. In one embodiment, the semiconductor device structure includes a first channel layer formed of a first material, wherein the first channel layer has a first width, and a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer and the second channel layer, and a gate electrode layer disposed on the gate dielectric layer.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 24, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Ching WANG, Wei-Yang LEE, Ming-Chang WEN, Jo-Tzu HUNG, Wen-Hsing HSIEH, Kuan-Lun CHENG
  • Multi-gate devices and fabricating the same with etch rate modulation
    Patent number: 11282943
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a fin structure having first semiconductor layers and second semiconductor layers alternately stacked, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region thereby forming an opening exposing at least one second semiconductor layer. The method also includes implanting an etch rate modifying species into the at least one second semiconductor layer though the opening thereby forming an implanted portion of the at least one second semiconductor layer. The method further includes selectively etching the implanted portion of the at least one second semiconductor layer, recessing end portions of the first semiconductor layers exposed in the opening, and forming an S/D epitaxial layer in the opening.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Method for identifying compound for inhibiting an activity of a histone lysine demethylase
    Patent number: 11279966
    Abstract: A method for identifying a compound that inhibits an activity of a histone lysine demethylase, in which the compound interacts with three sites of a pocket of the histone lysine demethylase generated by using a computer program, an alpha-ketoglutarate (AKG), a methylated lysine, and a NIQ.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: March 22, 2022
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Wen-Ching Wang, Hsing-Jien Kung, Chia-Han Chu, Jing-Moon Yang
  • Reflective display device
    Patent number: 11269234
    Abstract: A reflective display device includes a thin-film transistor (TFT) array substrate, a front panel laminate (FPL), a front protection sheet, a back protection sheet, a light blocking layer, and a light source. The front panel laminate is located on the TFT array substrate, and has a transparent conductive layer and a display medium layer. The display medium layer is located between the transparent conductive layer and the TFT array substrate. The front protection sheet is located on the front panel laminate. The back protection sheet is located below the TFT array substrate. The light blocking layer at least covers a lateral surface of the back protection sheet. The light source faces toward a lateral surface of the front panel laminate, a lateral surface of the TFT array substrate, and the lateral surface of the back protection sheet.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: March 8, 2022
    Assignee: E Ink Holdings Inc.
    Inventors: Chia-Chi Chang, Chih-Chun Chen, Chi-Ming Wu, Yi-Ching Wang, Jia-Hung Chen, Cheng-Hsien Lin
  • Super-fast transient response (STR) AC/DC converter for high power density charging application
    Patent number: 11258270
    Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 22, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Pei-Lun Huang, Yu-Ming Chen, Tien-Chi Lin, Jung-Pei Cheng, Yueh-Ping Yu, Zhi-Qiang Niu, Xiaotian Zhang, Long-Ching Wang
  • Display device
    Patent number: 11227557
    Abstract: The present disclosure provides a display device. The display device includes a substrate, a pixel array, a circuit bridge structure, a first trace region, a second trace region, and a display film layer. The pixel array is located on the substrate. The circuit bridge structure is located at one side of the pixel array. The first trace region is located between the pixel array and a first side of the circuit bridge structure. The second trace region is located at a second side opposite to the first side. The display film layer is located on the pixel array, and an orthogonal projection of the display film layer on the substrate is spaced apart from an orthogonal projection of the circuit bridge structure on the substrate.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: January 18, 2022
    Assignee: E Ink Holdings Inc.
    Inventors: Chia-Chi Chang, Chih-Chun Chen, Chi-Ming Wu, Yi-Ching Wang, Jia-Hung Chen
  • Polysaccharide-protein conjugates utilizing diphtheria toxin fragment B as a carrier
    Patent number: 11219680
    Abstract: The present invention provides immunogenic compositions having one or more polysaccharide-protein conjugates in which polysaccharides obtained from bacterial capsules are conjugated to diphtheria toxin fragment B (DTFB) or a variant thereof. The immunogenic compositions may be multivalent pneumococcal polysaccharide conjugate compositions in which polysaccharides from one or more Steptococcus pneumoniae serotypes are conjugated to diphtheria toxin fragment B (DTFB) and, optionally, additional polysaccharides from one or more different Steptococcus pneumoniae serotypes are conjugated to one or more other carrier proteins.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: January 11, 2022
    Assignee: Merck Sharp & Dohme Corp.
    Inventors: John E. MacNair, Michael A. Winters, Thomas Svab, Sheng-Ching Wang, William J. Smith, Cecilia Giovarelli
  • Semiconductor package having enlarged gate pad and method of making the same
    Patent number: 11222858
    Abstract: A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: January 11, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Yueh-Se Ho, Long-Ching Wang, Xiaotian Zhang, Zhiqiang Niu
  • SEMICONDUCTOR PACKAGE HAVING ENLARGED GATE PAD AND METHOD OF MAKING THE SAME
    Publication number: 20210398926
    Abstract: A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 23, 2021
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Yueh-Se Ho, Long-Ching Wang, Xiaotian Zhang, Zhiqiang Niu
  • Multi-Gate Devices and Fabricating the Same with Etch Rate Modulation
    Publication number: 20210391443
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a fin structure having first semiconductor layers and second semiconductor layers alternately stacked, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region thereby forming an opening exposing at least one second semiconductor layer. The method also includes implanting an etch rate modifying species into the at least one second semiconductor layer though the opening thereby forming an implanted portion of the at least one second semiconductor layer. The method further includes selectively etching the implanted portion of the at least one second semiconductor layer, recessing end portions of the first semiconductor layers exposed in the opening, and forming an S/D epitaxial layer in the opening.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Nanowire stack GAA device and methods for producing the same
    Patent number: 11201243
    Abstract: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chansyun David Yang, Han-Yu Lin, Chun-Yu Chen, Chih-Ching Wang, Fang-Wei Lee, Tze-Chung Lin, Li-Te Lin, Gwan-Sin Chang, Pinyen Lin