Patents by Inventor Chou Tsai

Chou Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220382957
    Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Hui-Zhong ZHUANG, Meng-Kai HSU, Pin-Dai SUE, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU, Jung-Chou TSAI
  • Publication number: 20220344293
    Abstract: An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mth row extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The second pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nth conductive lines.
    Type: Application
    Filed: July 12, 2022
    Publication date: October 27, 2022
    Inventors: JUNG-CHOU TSAI, FONG-YUAN CHANG, PO-HSIANG HUANG, CHIN-CHOU LIU, YI-KAN CHENG
  • Patent number: 11404361
    Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: August 2, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Yi-Hsuan Liu, Mei-Chi Chen, Ying-Chou Tsai
  • Publication number: 20220087516
    Abstract: The endoscopic device includes a main member having a front slot and a shaft member having a spiral strip selectively running through the slot. The spiral strip is connected to a rotational element whose front end is provided with an optical element. A camera support element is extended from the main member and a camera element is supported by the camera support element. By running the spiral strip through the slot to turn the rotational element and the optical element, a viewing direction of the camera element is altered by the optical element.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventors: Tsang-Chou Tsai, John Huang
  • Publication number: 20220083014
    Abstract: The present invention provides a remote-operated intelligent microcomputer light switch that can fully replace conventional switches, which can execute the on/off function of general wall switches, and different remote settings and operations can be performed through a smart device. The switch comprises an ornamental panel; an operation core; a button area providing touch switch function, combined with a LED indicator light to display status, an embedded battery supplies power for persistent operation, and contacts identical with general wall switches; a control pedestal, embedded with a control circuit abutting connecting terminals on the operation core to obtain control signal, and the high and low tension circuits are completely isolated to avoid the risk of electric shock. There are foolproof locking holes in the upper and lower parts of the framework of the control pedestal, which can fix the operation core in a fixed direction to avoid vertical reversal.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 17, 2022
    Inventor: Chou Tsai-Fu
  • Patent number: 11239179
    Abstract: A semiconductor package includes a substrate having thereon a high-frequency chip and a circuit component susceptible to high-frequency signal interference; a ground pad on the and between the high-frequency chip and the circuit component; a metal-post reinforced glue wall on the ground pad; a molding compound surrounding the metal-post reinforced glue wall and surrounding the high-frequency chip and the circuit component; and a conductive layer disposed on the molding compound and in contact with the metal-post reinforced glue wall. The metal-post reinforced glue wall comprises first metal posts and glue attached to the first metal posts. An interface between a base of each of the first metal posts and the ground pad has a root mean square (RMS) roughness that is less than 1.0 micrometer.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: February 1, 2022
    Inventors: Shiann-Tsong Tsai, Hsien-Chou Tsai, Hsien-Wei Tsai, Yen-Mei Tsai Huang
  • Patent number: 11211340
    Abstract: A semiconductor package includes a substrate having a semiconductor chip disposed on a top surface of the substrate, a ground ring surrounding the semiconductor chip on the top surface of the substrate, a metal-post reinforced glue wall disposed on the ground ring to surround the semiconductor chip, and a molding compound disposed only inside the metal-post reinforced glue wall and covering the semiconductor chip. The metal-post reinforced glue wall comprises a magnetic or magnetizable filler so as to form an active electro-magnetic compatibility (EMC) shielding.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: December 28, 2021
    Inventors: Shiann-Tsong Tsai, Hsien-Chou Tsai, Hsien-Wei Tsai, Yen-Mei Tsai Huang
  • Patent number: 11175519
    Abstract: A structure includes a goggles body including rim sections and temple sections, an imaging device arranged between the rim sections, light-emitting elements arranged on an outer edge of the rim sections, and an electricity supply element, a control module, a storage device, and a data transmission device arranged in the temple sections. A server host device is also included. The server host device includes a wireless transmission module, a recognition processing module, and a driving processing element. As such, a surgeon may wear the goggles body in a surgical operation to acquire supplemented lighting in the eyesight range and a function of recording the entire process of the surgical operation. The surgeon may take a motion of a predetermined hand gesture to issue a control instruction corresponding thereto in order to execute the control instruction on a medical device to allow the surgeon to control hardware necessary for the operation.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: November 16, 2021
    Assignee: BROAD PERSPECT BIOMEDICAL TECHNOLOGY CO., LTD.
    Inventors: Tsang-Chou Tsai, John Huang
  • Patent number: 11114393
    Abstract: An electronic package and a method for fabricating the same are provided. A plurality of electronic components are disposed in a packaging structure. At least one antenna structure is stacked via a plurality of conductive elements on the packaging structure. The antenna structure is electrically connected to at least one of the electronic components. The electronic components have different radio frequencies. In mass production, the antenna structures of different antenna types are stacked on the packaging structure, and a radio frequency product of various frequencies can be produced. Radio frequency chips of different frequencies need not be fabricated into a variety of individual packaging modules. Therefore, the production cost is reduced, and the production speed is increased.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: September 7, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wen-Jung Tsai, Ching-Chia Chen, Ying-Chou Tsai
  • Publication number: 20210109380
    Abstract: A structure includes a goggles body including rim sections and temple sections, an imaging device arranged between the rim sections, light-emitting elements arranged on an outer edge of the rim sections, and an electricity supply element, a control module, a storage device, and a data transmission device arranged in the temple sections. A server host device is also included. The server host device includes a wireless transmission module, a recognition processing module, and a driving processing element. As such, a surgeon may wear the goggles body in a surgical operation to acquire supplemented lighting in the eyesight range and a function of recording the entire process of the surgical operation. The surgeon may take a motion of a predetermined hand gesture to issue a control instruction corresponding thereto in order to execute the control instruction on a medical device to allow the surgeon to control hardware necessary for the operation.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 15, 2021
    Inventors: Tsang-Chou Tsai, John Huang
  • Publication number: 20210066173
    Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 4, 2021
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Yi-Hsuan Liu, Mei-Chi Chen, Ying-Chou Tsai
  • Publication number: 20210066223
    Abstract: An interconnect structure includes a plurality of first pads, a plurality of second pads, a plurality of first conductive lines in a first layer, a plurality of second conductive lines in a second layer, and a plurality of nth conductive lines in an nth layer. The first pads and the second pads respectively are grouped into a first, a second and an nth group. Each of the first pads in first group is connected to one of the second pads in the first group by one of the first conductive lines. Each of the first pads in the second group is connected to one of the second pads in the second group by one of the second conductive lines. Each of the first pads in the nth group is connected to one of the second pads in the nth group by one of the nth conductive lines.
    Type: Application
    Filed: May 26, 2020
    Publication date: March 4, 2021
    Inventors: JUNG-CHOU TSAI, FONG-YUAN CHANG, PO-HSIANG HUANG, CHIN-CHOU LIU, YI-KAN CHENG
  • Patent number: 10923435
    Abstract: A semiconductor package includes a substrate having at least one semiconductor chip on a top surface of the substrate; a ground ring, on the top surface of the substrate, surrounding the at least one semiconductor chip; a metal-post reinforced glue wall disposed on the ground ring, surrounding the at least one semiconductor chip; a molding compound surrounding the at least one semiconductor chip, wherein a rear surface of the at least one semiconductor chip is flush with an upper surface of the molding compound; a conductive layer disposed on the molding compound and in direct contact with the rear surface of the semiconductor chip and the metal-post reinforced glue wall; a solder layer disposed on the conductive layer; and a heat sink disposed on the solder layer.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: February 16, 2021
    Inventors: Shiann-Tsong Tsai, Hsien-Chou Tsai, Hsien-Wei Tsai, Yen-Mei Tsai Huang
  • Patent number: 10903564
    Abstract: A communication apparatus is provided. A retaining wall structure electrically connected with a ground plane is disposed between a main circuit board and an antenna. A retaining wall part of the retaining wall structure has a thickness. A distance between the retaining wall part and the main circuit board is a first distance, and a distance between the retaining wall part and the antenna and is a second distance. A distance between the retaining wall and a shielding metal plate is a third distance. The projection of the antenna projected toward the retaining wall in the orthogonal projection direction falls on the retaining wall part.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: January 26, 2021
    Assignee: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Huan-Chia Chang, Chao-Hsu Wu, Shih-Keng Huang, Chia-Chou Tsai, Yu-Yi Chu
  • Patent number: 10896880
    Abstract: A semiconductor package includes a substrate. A high-frequency chip and a circuit component susceptible to high-frequency interference are disposed on a top surface of the substrate. A first ground ring is disposed on the substrate around the high-frequency chip. A first metal-post reinforced glue wall is disposed on the first ground ring to surround the high-frequency chip. A second ground ring is disposed on the top of the substrate around the circuit component. A second metal-post reinforced glue wall is disposed on the second ground ring to surround the circuit component. Mold-flow channels are disposed in the first and second metal-post reinforced glue walls. A molding compound covers at least the high-frequency chip and the circuit component. A conductive layer is disposed on the molding compound and is coupled to the first metal-post reinforced glue wall and/or the second metal-post reinforced glue wall.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: January 19, 2021
    Inventors: Shiann-Tsong Tsai, Hsien-Chou Tsai, Hsien-Wei Tsai, Yen-Mei Tsai Huang
  • Patent number: 10872847
    Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 22, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Yi-Hsuan Liu, Mei-Chi Chen, Ying-Chou Tsai
  • Patent number: 10839516
    Abstract: A simulate segmentation method of cylinder and pie cake digital models utilizes a three-dimensional model and a reference point to cope with various shapes of the nuclear reactor structures. The segmentation simulation of the nuclear reactor structure is conducted with genetic algorithm. The segmentation simulation of the nuclear reactor structure is achieved by using the genetic algorithm to perform a double selection mechanism on the cross-sectional area of the nuclear reactor structure to select the optimal configuration of the segmentation, thus minimizing the cross-sectional areas of the nuclear reactor structure. The cutter segments the nuclear reactor structure based on the optimal configuration of the segmentation, thereby achieving the purpose of minimizing the attrition rate of a cutter and segmenting the nuclear reactor structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 17, 2020
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN
    Inventors: Yu-Hsiang Hung, Chung-Hao Huang, Shiang-Fong Chen, Po-Chou Tsai
  • Patent number: 10833394
    Abstract: An electronic package and a method for fabricating the same are provided. An antenna frame, a first electronic component, and a second electronic component electrically connected to the antenna frame are disposed on a lower side of a carrying structure. An antenna structure is disposed on an upper side of the carrying structure and is electrically connected to the first electronic component. Therefore, two different types of antennas are integrated into an identical electronic package. Such the electronic package bonded to a circuit can transmit signals with two different wavelengths, even if the electronic package does not have any area increased.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: November 10, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wen-Jung Tsai, Mao-Hua Yeh, Chih-Hsien Chiu, Ying-Chou Tsai, Chun-Chi Ke
  • Publication number: 20200343196
    Abstract: A semiconductor package includes a substrate having thereon a high-frequency chip and a circuit component susceptible to high-frequency signal interference; a ground pad on the and between the high-frequency chip and the circuit component; a metal-post reinforced glue wall on the ground pad; a molding compound surrounding the metal-post reinforced glue wall and surrounding the high-frequency chip and the circuit component; and a conductive layer disposed on the molding compound and in contact with the metal-post reinforced glue wall. The metal-post reinforced glue wall comprises first metal posts and glue attached to the first metal posts. An interface between a base of each of the first metal posts and the ground pad has a root mean square (RMS) roughness that is less than 1.0 micrometer.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventors: Shiann-Tsong Tsai, Hsien-Chou Tsai, Hsien-Wei Tsai, Yen-Mei Tsai Huang
  • Publication number: 20200328166
    Abstract: An electronic package and a method for fabricating the same are provided. A plurality of electronic components are disposed in a packaging structure. At least one antenna structure is stacked via a plurality of conductive elements on the packaging structure. The antenna structure is electrically connected to at least one of the electronic components. The electronic components have different radio frequencies. In mass production, the antenna structures of different antenna types are stacked on the packaging structure, and a radio frequency product of various frequencies can be produced. Radio frequency chips of different frequencies need not be fabricated into a variety of individual packaging modules. Therefore, the production cost is reduced, and the production speed is increased.
    Type: Application
    Filed: August 7, 2019
    Publication date: October 15, 2020
    Inventors: Wen-Jung Tsai, Ching-Chia Chen, Ying-Chou Tsai