Abstract: An electronic package and a method for fabricating the same are provided. An antenna frame, a first electronic component, and a second electronic component electrically connected to the antenna frame are disposed on a lower side of a carrying structure. An antenna structure is disposed on an upper side of the carrying structure and is electrically connected to the first electronic component. Therefore, two different types of antennas are integrated into an identical electronic package. Such the electronic package bonded to a circuit can transmit signals with two different wavelengths, even if the electronic package does not have any area increased.

Abstract: A semiconductor package includes a substrate having at least one semiconductor chip on a top surface of the substrate; a ground ring, on the top surface of the substrate, surrounding the at least one semiconductor chip; a metal-post reinforced glue wall disposed on the ground ring, surrounding the at least one semiconductor chip; a molding compound surrounding the at least one semiconductor chip, wherein a rear surface of the at least one semiconductor chip is flush with an upper surface of the molding compound; a conductive layer disposed on the molding compound and in direct contact with the rear surface of the semiconductor chip and the metal-post reinforced glue wall; a solder layer disposed on the conductive layer; and a heat sink disposed on the solder layer.

Abstract: A semiconductor package includes a substrate. A high-frequency chip and a circuit component susceptible to high-frequency interference are disposed on a top surface of the substrate. A first ground ring is disposed on the substrate around the high-frequency chip. A first metal-post reinforced glue wall is disposed on the first ground ring to surround the high-frequency chip. A second ground ring is disposed on the top of the substrate around the circuit component. A second metal-post reinforced glue wall is disposed on the second ground ring to surround the circuit component. Mold-flow channels are disposed in the first and second metal-post reinforced glue walls. A molding compound covers at least the high-frequency chip and the circuit component. A conductive layer is disposed on the molding compound and is coupled to the first metal-post reinforced glue wall and/or the second metal-post reinforced glue wall.

Abstract: A semiconductor package includes a substrate having a semiconductor chip disposed on a top surface of the substrate, a ground ring surrounding the semiconductor chip on the top surface of the substrate, a metal-post reinforced glue wall disposed on the ground ring to surround the semiconductor chip, and a molding compound disposed only inside the metal-post reinforced glue wall and covering the semiconductor chip. The metal-post reinforced glue wall comprises a magnetic or magnetizable filler so as to form an active electro-magnetic compatibility (EMC) shielding.

Abstract: The present disclosure illustrates a hydrogen water generator, a micro/nano hydrogen bubble water generator and a micro/nano hydrogen bubble water production method. The hydrogen water generator of the present disclosure receives water and hydrogen gas, and five sections are formed inside the main body of the hydrogen water generator, so as to mix the hydrogen gas and the water to produce hydrogen water, without using a compressor to pressure the hydrogen gas. The water flows to a pressuring section via a liquid input section, and is pressured by a pressuring section and the pressured water further flows to a draining and mixing section to be mixed with the hydrogen gas. The water mixed with hydrogen gas flows to a decompressing section to be decompressed, and then passes a hydrogen water output section to output hydrogen water with micro/nano hydrogen bubbles.

Abstract: Disclosed are methods for designing semiconductor devices, conductive layer patterns, and interconnection layer patterns including the operations of analyzing an initial semiconductor design layout to identify excessive open spaces between adjacent conductive elements or lines within an interconnection layer pattern, selecting or generating a dummy pattern to fill a portion of the open space, and generating a modified semiconductor design layout that incorporates the dummy pattern into first interconnection layer pattern to reduce the open space.

Abstract: A simulate segmentation method of cylinder and pie cake digital models utilizes a three-dimensional model and a reference point to cope with various shapes of the nuclear reactor structures. The segmentation simulation of the nuclear reactor structure is conducted with genetic algorithm. The segmentation simulation of the nuclear reactor structure is achieved by using the genetic algorithm to perform a double selection mechanism on the cross-sectional area of the nuclear reactor structure to select the optimal configuration of the segmentation, thus minimizing the cross-sectional areas of the nuclear reactor structure. The cutter segments the nuclear reactor structure based on the optimal configuration of the segmentation, thereby achieving the purpose of minimizing the attrition rate of a cutter and segmenting the nuclear reactor structure.

Abstract: A communication apparatus is provided. A retaining wall structure electrically connected with a ground plane is disposed between a main circuit board and an antenna. A retaining wall part of the retaining wall structure has a thickness. A distance between the retaining wall part and the main circuit board is a first distance, and a distance between the retaining wall part and the antenna and is a second distance. A distance between the retaining wall and a shielding metal plate is a third distance. The projection of the antenna projected toward the retaining wall in the orthogonal projection direction falls on the retaining wall part.

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.

Abstract: An electronic package is provided, including an electronic component, a redistribution structure formed on the electronic component, a plurality of conductive posts bonded to the redistribution structure, and a redistribution layer bonded to the conductive posts. As such, the electronic component that meets the requirement of miniaturization can be electrically connected to an electronic device through the redistribution structure, the conductive posts and the redistribution layer.

Abstract: A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.

Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.

Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.

Abstract: A package structure is provided, including a carrier, an electronic component disposed on the carrier and having a sensing area, an encapsulant formed on the carrier and encapsulating the electronic component and the sensing area, and a conductive layer formed on the encapsulant with the sensing area of the electronic component free from being covered by the conductive layer. The encapsulant prevents a user's finger from being in direct contact with the sensing area so as to protect the sensing area from being damaged and hence ensure normal operation of the electronic component.

Abstract: Fuse structures and forming and operation methods thereof are disclosed. One of the fuse structures includes a dielectric strip and a fuse strip extending in different directions. The dielectric strip is sandwiched by a first conductive strip and a second conductive strip. The fuse strip is insulated from each of the first conductive strip and the second conductive strip and has a blowing region corresponding to the dielectric strip.

Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.

Abstract: A package structure is provided, including a carrier, an electronic component disposed on the carrier and having a sensing area, an encapsulant formed on the carrier and encapsulating the electronic component and the sensing area, and a conductive layer formed on the encapsulant with the sensing area of the electronic component free from being covered by the conductive layer. The encapsulant prevents a user's finger from being in direct contact with the sensing area so as to protect the sensing area from being damaged and hence ensure normal operation of the electronic component.

Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.

Abstract: A positioning structure includes a locating member, a movable mechanism mounted in the locating member for the connection of a mop and movable up and down relative to the locating member, and a positioning mechanism mounted in the locating member for stopping against the positioning mechanism upon connection of a mop to the movable mechanism to support the mop stably in position for dehydration through a spining action after movement of the movable mechanism to the top side of the locating member.