Patents by Inventor Chou Tsai

Chou Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180000310
    Abstract: A positioning structure includes a locating member, a movable mechanism mounted in the locating member for the connection of a mop and movable up and down relative to the locating member, and a positioning mechanism mounted in the locating member for stopping against the positioning mechanism upon connection of a mop to the movable mechanism to support the mop stably in position for dehydration through a spining action after movement of the movable mechanism to the top side of the locating member.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventor: Chen-Chou TSAI
  • Patent number: 9805979
    Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: October 31, 2017
    Assignee: Siliconware Precision Industires Co., Ltd.
    Inventors: Shao-Tzu Tang, Chang-Yi Lan, Ying-Chou Tsai
  • Publication number: 20170294372
    Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventors: Chia-Cheng Chen, Chi-Ching Ho, Shao-Tzu Tang, Yu-Che Liu, Ying-Chou Tsai
  • Publication number: 20170273185
    Abstract: A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.
    Type: Application
    Filed: June 6, 2017
    Publication date: September 21, 2017
    Inventors: Shao-Tzu Tang, Ying-Chou Tsai
  • Publication number: 20170191412
    Abstract: A hydrogen carbon cleaning method for a vehicle is provided, which includes the following steps. First, a reformer is provided. Then, high purity hydrogen is provided by the reformer. Next, a hydrogen carbon cleaning process is performed on a vehicle with the high purity hydrogen.
    Type: Application
    Filed: June 17, 2016
    Publication date: July 6, 2017
    Inventors: Yu-Chou Tsai, Liam-Yung Sung, Jung-Kuei Chang, Li-Chih Chen, Jian-Kai Wang
  • Patent number: 9699910
    Abstract: A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: July 4, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-tzu Tang, Ying-Chou Tsai
  • Publication number: 20170140891
    Abstract: Fuse structures and forming and operation methods thereof are disclosed. One of the fuse structures includes a dielectric strip and a fuse strip extending in different directions. The dielectric strip is sandwiched by a first conductive strip and a second conductive strip. The fuse strip is insulated from each of the first conductive strip and the second conductive strip and has a blowing region corresponding to the dielectric strip.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Chia-Chou Tsai, Mu-Yi Lin, Tzy-Kuang Lee
  • Publication number: 20170047230
    Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.
    Type: Application
    Filed: October 14, 2016
    Publication date: February 16, 2017
    Inventors: Chi-Ching Ho, Ying-Chou Tsai, Sheng-Che Huang
  • Publication number: 20170033037
    Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.
    Type: Application
    Filed: October 14, 2016
    Publication date: February 2, 2017
    Inventors: Chi-Ching Ho, Ying-Chou Tsai, Sheng-Che Huang
  • Patent number: 9362217
    Abstract: A method for fabricating a POP structure is disclosed. First, a first package is provided, which has: a dielectric layer; a stacked circuit layer embedded in the dielectric layer and exposed from upper and lower surfaces of the dielectric layer; a plurality of conductive posts and a semiconductor chip disposed on the upper surface of the dielectric layer and electrically connected to the stacked circuit layer; and an encapsulant formed on upper surface of the dielectric layer for encapsulating the semiconductor chip and the conductive posts and having a plurality of openings for exposing top ends of the conductive posts. Then, a second package is disposed on the encapsulant and electrically connected to the conductive posts. The formation of the conductive posts facilitates to reduce the depth of the openings of the encapsulant, thereby reducing the fabrication time and increasing the production efficiency and yield.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: June 7, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pang-Chun Lin, Wei-Ping Wang, Chun-Yuan Li, Shao-tzu Tang, Ying-Chou Tsai
  • Publication number: 20160133593
    Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.
    Type: Application
    Filed: February 18, 2015
    Publication date: May 12, 2016
    Inventors: Shao-Tzu Tang, Chang-Yi Lan, Ying-Chou Tsai
  • Patent number: 9269816
    Abstract: A thin film transistor (TFT) is provided, which includes a substrate, a first gate layer, an insulation layer, a first source/drain layer, a second source/drain layer, a semiconductor layer, a passivation layer and a second gate layer. The first gate layer is disposed on the substrate. The insulation layer is disposed on the first gate layer. The first source/drain layer is disposed on the insulation layer. The second source/drain layer is disposed on the insulation layer. The semiconductor layer is disposed on the insulation layer and covers the first source/drain layer and the second source/drain layer. The passivation layer is disposed on the insulation layer and covers the semiconductor layer. The second gate layer is disposed on the passivation layer and contacts the first gate layer through a via so that the two gate layers keep a same voltage level.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: February 23, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Kuan-Yi Lin, Fang-An Shu, Yao-Chou Tsai, Tzung-Wei Yu
  • Patent number: 9265154
    Abstract: A fabrication method of a packaging substrate is provided, which includes the steps of: forming first conductive portions on a carrier; sequentially forming a conductive post and an alignment layer on each of the first conductive portions; forming an encapsulant on the carrier for encapsulating the first conductive portions, the conductive posts and the alignment layers; forming a conductive via on each of the alignment layers in the encapsulant and forming second conductive portions on the conductive vias and the encapsulant; and removing the carrier. Each of the first conductive portions and the corresponding conductive post, the alignment layer and the conductive via form a conductive structure. The alignment layer has a vertical projection area larger than those of the conductive post and the conductive via to thereby reduce the size of the conductive post and the conductive via, thus increasing the wiring density and the electronic element mounting density.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: February 16, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Chi-Ching Ho, Ying-Chou Tsai
  • Publication number: 20150366060
    Abstract: A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.
    Type: Application
    Filed: August 7, 2014
    Publication date: December 17, 2015
    Inventors: Shao-tzu Tang, Ying-Chou Tsai
  • Publication number: 20150305162
    Abstract: A fabrication method of a packaging substrate is provided, which includes the steps of: forming first conductive portions on a carrier; sequentially forming a conductive post and an alignment layer on each of the first conductive portions; forming an encapsulant on the carrier for encapsulating the first conductive portions, the conductive posts and the alignment layers; forming a conductive via on each of the alignment layers in the encapsulant and forming second conductive portions on the conductive vias and the encapsulant; and removing the carrier. Each of the first conductive portions and the corresponding conductive post, the alignment layer and the conductive via form a conductive structure. The alignment layer has a vertical projection area larger than those of the conductive post and the conductive via to thereby reduce the size of the conductive post and the conductive via, thus increasing the wiring density and the electronic element mounting density.
    Type: Application
    Filed: August 18, 2014
    Publication date: October 22, 2015
    Inventors: Shao-tzu Tang, Chi-Ching Ho, Ying-Chou Tsai
  • Patent number: 9165789
    Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: October 20, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Ching Ho, Yu-Chih Yu, Ying-Chou Tsai
  • Patent number: 9112063
    Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: August 18, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wei Chung Hsiao, Chun Hsien Lin, Yu Cheng Pai, Liang Yi Hung, Ming Chen Sun, Shao Tzu Tang, Ying Chou Tsai, Chang Yi Lan
  • Patent number: 9077491
    Abstract: Intelligent technique is an effective method to perform the network resource management. A three layer cascade adaptive neural fuzzy inference system (ANFIS) based intelligent controller is proposed for the mobile wireless network to optimize the maximum average throughput, minimum transmit power and interference for multimedia call services. The proposed intelligent controller is designed with a three layer cascade architecture, which mainly contains an ANFIS rate controller (ARC) in the first layer, an ANFIS power controller (APC) in the second layer and an ANFIS interference controller (AIC) in the third layer. The design aim of the proposed three layer cascade ANFIS cognitive engine is maximizing the average throughput of the mobile wireless network, while minimizing the transmit power and interference power.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: July 7, 2015
    Assignee: YUAN ZE UNIVERSITY
    Inventors: Jeich Mar, Kuei-Chou Tsai, Yu-Ting Wang
  • Publication number: 20150187603
    Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.
    Type: Application
    Filed: March 10, 2015
    Publication date: July 2, 2015
    Inventors: Chi-Ching Ho, Yu-Chih Yu, Ying-Chou Tsai
  • Patent number: 9069131
    Abstract: A transfer print structure is provided. The transfer print structure comprises a substrate; a color ink layer including a functional region; and an adhesive device combining the functional region with the substrate.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: June 30, 2015
    Assignee: E INK HOLDINGS INC.
    Inventors: Fang-An Shu, Ted-Hong Shinn, Yao-Chou Tsai, Wen-Chung Tang