Patents by Inventor Chou

Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11834867
    Abstract: An anti-theft lock includes an engaging member arranged on a chassis, a latch module including a connecting member and a latch coupled to the connecting member, a fixing module coupled to the connecting member, a magnetic module arranged on the top cover and used to cooperate with the fixing module to control movement of the connecting member, and an unlocking mechanism including magnetic members. The connecting member is movably arranged on a top cover. The latch is engaged with or separated from the engaging member through movement of the connecting member. The magnetic members are attracted to or repelled from the magnetic module so that the magnetic module fixes or loosens the connecting member. When the connecting member can move, the latch is disengaged from and separated from the engaging member.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: December 5, 2023
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Tung-Ho Shih, Hung-Wei Chen, Wei-Chung Chou, Ming-Heng Lu
  • Patent number: 11838000
    Abstract: Aspects of the present disclosure provide a method for regulating an integration current of a sensing amplifier. The sensing amplifier includes a first input transistor and a second input transistor, wherein a source of the first input transistor and a source of the second input transistor are coupled to a source node. The method includes pulling a current from or sourcing the current to the source node, measuring the integration current, comparing the measured integration current with a reference signal, and adjusting the current pulled from or sourced to the source node based on the comparison.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: December 5, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Todd Morgan Rasmus, Shih-Wei Chou
  • Patent number: 11832971
    Abstract: A wearable device utilizing flexible electronics is disclosed. The wearable device may comprise a flexible matrix material and may include sensors for measuring biometric measurements of an individual, an accelerometer for measuring an acceleration of a body part to which the wearable device is attached, a wireless transmitter, a flexible power source, and a microcontroller. During an activity, the microcontroller may receive signals from the sensors including the biometric measurements, and signals from the accelerometer including acceleration and force measurements associated with the individual. The microcontroller may convert the signals into digital signals and transmit the signals to a computing device for analysis. The computing device may analyze the digital signals to determine a performance metric for the individual. The performance metric may be compared to baseline data for the individual to determine a fatigue level, injury risk, or an adjustment to be made by the individual during the activity.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: December 5, 2023
    Assignee: Advancing Technologies, LLC
    Inventors: Ricky Alphonse, Kelsey Melrose, Catherine Chou, Noah Schimmel, Ramamurthy Siripuram, Anthony Tran, Britny Farahdel, Dalton Smith, Danice Wang, Kunal Mehan, Theodore Virtue
  • Patent number: 11837552
    Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: December 5, 2023
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
  • Patent number: 11833642
    Abstract: The invention relates to a power tool with an electrically controlled commutating assembly comprising: an electrically controlled commutating assembly and a control unit; the electrically controlled commutating assembly has an electromagnetic unit; the electromagnetic unit is capable of performing a change in displacement due to electromagnetic action; the control unit has a control member, the control member is capable of changing a working direction of a power tool, and displacement of the electromagnetic unit is capable of actuating the control member of the control unit to make the power tool switch the working direction.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: December 5, 2023
    Assignee: TECHWAY INDUSTRIAL CO., LTD.
    Inventors: Fu-Hsiang Chung, Hong Fang Chen, Wei-Ting Chen, Shih-Wei Hung, Kuo Chou Li
  • Patent number: 11837300
    Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: December 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou, Yih Wang
  • Patent number: 11838100
    Abstract: Some of the present embodiments provide a method for search space monitoring by a user equipment (UE). The method includes monitoring a first search space and a second search space. The method may receive, from a serving base station, a search space monitoring (de)activation message, which is transmitted by the serving base station of the UE, by monitoring the first search space. The method deactivates the monitoring of the second search space based on the received search space (de)activation message. In some of the present embodiments, each of the first and second search spaces includes one or more physical downlink control channel (PDCCH) candidates, and monitoring the first search space and the second search space comprises decoding the one or more PDCCH candidates in each of the first search space and the second search space.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 5, 2023
    Assignee: FG Innovation Company Limited
    Inventors: Yung-Lan Tseng, Hung-Chen Chen, Chie-Ming Chou
  • Patent number: 11837622
    Abstract: An image sensor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a protection oxide film, and a nitride hard mask. The gate dielectric layer is over the semiconductor substrate. The gate electrode is over the gate dielectric layer. An entirety of a first portion of the gate dielectric layer directly under the gate electrode is of uniform thickness. The protection oxide film is in contact with a top surface of the gate electrode. The gate dielectric layer extends beyond a sidewall of the protection oxide film. The nitride hard mask is in contact with a top surface of the protection oxide film.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei Chia, Chun-Hao Chou, Kai-Chun Hsu, Kuo-Cheng Lee, Shyh-Fann Ting
  • Patent number: 11835951
    Abstract: Systems and methods for predicting object motion and controlling autonomous vehicles are provided. In one example embodiment, a computer implemented method includes obtaining state data indicative of at least a current or a past state of an object that is within a surrounding environment of an autonomous vehicle. The method includes obtaining data associated with a geographic area in which the object is located. The method includes generating a combined data set associated with the object based at least in part on a fusion of the state data and the data associated with the geographic area in which the object is located. The method includes obtaining data indicative of a machine-learned model. The method includes inputting the combined data set into the machine-learned model. The method includes receiving an output from the machine-learned model. The output can be indicative of a plurality of predicted trajectories of the object.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: December 5, 2023
    Assignee: UATC, LLC
    Inventors: Nemanja Djuric, Vladan Radosavljevic, Thi Duong Nguyen, Tsung-Han Lin, Jeff Schneider, Henggang Cui, Fang-Chieh Chou, Tzu-Kuo Huang
  • Patent number: 11832946
    Abstract: System, methods, and other embodiments described herein relate to controlling display attributes within a visual interface for enhancing stimuli and responses of a user. In one embodiment, a method includes selecting display attributes related to a first layer of an image and a second layer of the image, wherein the image is associated with an interface to control a component. The method also includes oscillating, at a frequency, between first values of the display attributes for displaying the first layer. The method also includes oscillating, at a harmonic of the frequency, between second values of the display attributes for displaying the second layer in parallel with the first layer until detecting a selection associated with the interface.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: December 5, 2023
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Chungchih Chou, Muhamed Farooq, Ercan Mehmet Dede
  • Publication number: 20230386936
    Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 30, 2023
    Inventors: Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang
  • Publication number: 20230381382
    Abstract: The invention relates to biodegradable, magnesium alloys, compositions and composites, methods for their preparation and applications for their use as implantable medical devices in load-bearing conditions. The magnesium alloys are composed of alloying elements selected from yttrium, calcium, zirconium, zinc, and strontium, with the remainder being magnesium and impurities arising due to production, and preparation of the alloy by melting together the elements and casting the resulting melted mixture. In certain embodiments, the methods of preparation include solution treatment and hot extrusion.
    Type: Application
    Filed: June 1, 2023
    Publication date: November 30, 2023
    Applicant: UNIVERSITY OF PITTSBURGH - OF THE COMMONWEALTH SYSTEM OF HIGHER EDUCATION
    Inventors: PRASHANT N. KUMTA, ABHIJIT ROY, DA-TREN CHOU, DAEHO HONG, VIJAY S. GORANTLA
  • Publication number: 20230385522
    Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Hui-Zhong ZHUANG, Meng-Kai HSU, Pin-Dai SUE, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU, Jung-Chou TSAI
  • Publication number: 20230383399
    Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Inventors: Ming-Yi SHEN, Hsin-Lin WU, Yao-Fong DAI, Pei-Yuan TAI, Chin-Wei CHEN, Yin-Tun CHOU, Yuan-Hsin CHI, Sheng-Yuan LIN
  • Publication number: 20230386799
    Abstract: A focus ring for a plasma-based semiconductor processing tool is designed to provide and/or ensure etch rate uniformity across a wafer during a plasma etch process. The focus ring may include an angled inner wall that is angled away from a center of the focus ring to direct a plasma toward the wafer. The angle of the angled inner wall may be greater than approximately 130 degrees relative to the top surface of the wafer and/or may be less than approximately 50 degrees relative to an adjacent lower surface of the focus ring to reduce and/or eliminate areas of overlapping plasma on the wafer (which would otherwise cause non-uniform etch rates). Moreover, an inner diameter may be configured to be in a range of approximately 209 millimeters to 214 millimeters to further reduce and/or eliminate areas of overlapping plasma on the wafer.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Sheng-Chieh HUANG, Chang Kuang TSO, Chou Feng LEE, Chung-Hsiu CHENG, Jr-Sheng CHEN, Chun Yan CHEN, Chih-Hsien HSU, Chin-Tai HUNG
  • Publication number: 20230387169
    Abstract: A device includes a plurality of photodiode regions within a semiconductor substrate, a plurality of transistors, a plurality of deep trench isolation (DTI) structures, and a plurality of isolation structures. The transistors are over a front-side surface of the semiconductor substrate. The DTI structures extend a first depth from a backside surface of the semiconductor substrate into the semiconductor substrate. The isolation structures extend a second depth from the backside surface of the semiconductor substrate into the semiconductor substrate. The second depth is less than the first depth. From a plan view, each of the plurality of isolation structures has a triangular profile at the backside surface of the semiconductor substrate.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20230387153
    Abstract: A pixel sensor may include a layer stack to reduce and/or block the effects of plasma and etching on a photodiode and/or other lower-level layers. The layer stack may include a first oxide layer, a layer having a band gap that is approximately less than 8.8 electron-Volts (eV), and a second oxide layer. The layer stack may reduce and/or prevent the penetration and absorption of ultraviolet photons resulting from the plasma and etching processes, which may otherwise cause the formation of electron-hole pairs in the substrate in which the photodiode is included.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Wei-Lin CHEN, Ching-Chung SU, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20230387182
    Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Wei-Yu CHOU, Yang-Che CHEN, Chen-Hua LIN, Victor Chiang LIANG, Huang-Wen TSENG, Chwen-Ming LIU
  • Publication number: 20230387213
    Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Yu-Shan Lu, Hung-Ju Chou, Pei-Ling Gao, Chen-Hsuan Liao, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu
  • Publication number: 20230385839
    Abstract: Systems and methods for reducing false positives for financial transaction fraud monitoring using machine learning techniques. Using an original model for separating transactions into high risk and low risk categories for fraud, transactions falling into the high-risk category may be labeled as a false positive or a true positive. The labels and data associated with the transactions may be used to train two or more false positive reduction models (FPRMs) using iterative machine learning techniques. Once training is complete, a future transaction may be processed using the original model, and, if the original model indicates that the future transaction is high risk, data associated with the future transaction may be processed by the trained FPRM(s), which may determine whether the future transaction is at a high risk or a low risk of being fraudulent.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Applicant: Mastercard International Incorporated
    Inventors: Fariborz Nadi, Jose Qiu Chou, Yuanzheng Du