Abstract: Interlayer dielectric (ILD) layer(s) of a semiconductor device may be configured as a gate oxide for high-voltage transistors, and therefore additional process operations to deposit dedicated gate oxide layers are not needed. Moreover, additional processing operations to form the gate structures of the high-voltage fin-based PMOS transistors and high-voltage fin-based NMOS transistors are not needed in that middle end of line (MEOL process and back end of line (BEOL) processes can be used as the gate formation process of the high-voltage transistors.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure of a CMOS image sensor. The method includes providing a substrate; growing an epitaxial layer on the substrate; forming a barrier layer on the epitaxial layer; forming a trench extending into the epitaxial layer; oxidizing the epitaxial layer to form a liner layer; defining a region of a photodiode and a first dopant thickness; implanting dopants into the epitaxial layer around a sidewall of the trench to form a protective layer with a second dopant thickness less than the first dopant thickness; forming an oxide layer in the trench; performing an annealing operation to densify the oxide layer to form a densified oxide layer, wherein the protective layer, expanded from the second dopant thickness to a third dopant thickness less than the first dopant thickness, is kept spaced from the region; and forming the photodiode in the region.

Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

Abstract: A robotic procedure system for treating neurovasculature of a patient including a guide sheath, catheter system having a support catheter and a navigation catheter, and robotic drive system configured to drive the catheter system within a patient's vessel. The robotic drive system includes a cassette with at least a first set of rollers and at least a second set of rollers and a controller operatively coupled to the cassette. The first set of rollers is configured to engage a proximal control element of the support catheter and the second set of rollers configured to engage a proximal extension of the navigation catheter. The controller is configured to control the first set and second set of rollers so as to determine a magnitude of linear translation of the support catheter and a magnitude of linear translation of the navigation catheter. Related devices, systems, and methods are provided.

Abstract: A method for preparing a semiconductor device, includes: forming a first dielectric structure and a second dielectric structure over a semiconductor substrate; forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure; partially removing the conductive material to form a first bit line and a second bit line in the first opening; forming a first capacitor contact and a second capacitor contact in the first dielectric structure and the second dielectric structure, respectively; forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate; and forming a first capacitor and a second capacitor over the first capacitor contact and the second capacitor contact, respectively.

Abstract: A system (1) of an electronic lock (3) and an electronic key (2).

Abstract: A semiconductor structure includes a substrate, a first FET device and a second FET device. The substrate has a first region and a second region. The first FET device is in the first region, and the second FET device is in the second region. The first FET device includes a first isolation structure, a first gate electrode disposed over a portion of the first isolation structure, and a first gate dielectric layer between the substrate and the first gate electrode. The first gate dielectric layer has a first thickness. The second FET device includes a plurality of fin structures, a plurality of second isolation structures, a second gate electrode over the plurality of fin structures, and a second gate dielectric layer between the second gate electrode and the plurality of fin structures. The second gate dielectric layer has a second thickness. The second thickness is less than the first thickness.

Abstract: Methods of configuring a memory might include characterizing a read window budget for a programming operation of the memory as a function of a programming step voltage for a plurality of memory cell ages, determining a respective programming step voltage for each memory cell age of the plurality of memory cell ages in response to a desired read window budget, and storing data to the memory indicative of the determined respective programming step voltage for each memory cell age of the plurality of memory cell ages.

Abstract: In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.

Abstract: A method of making a golf club head includes interposing bonding tape between a first piece and a second piece of the golf club head such that the first piece is temporarily adhered to the second piece via a tackiness of the bonding tape. The method additionally includes positioning the first piece, the second piece, and the bonding tape, interposed between the first piece and the second piece, in a vacuum bag, and reducing a pressure within the vacuum bag, relative to a pressure external to the vacuum bag, such that the vacuum bag collapses onto the first piece and the second piece and compresses the bonding tape between the first piece and the second piece. The method also includes heating the bonding tape, at least to a curing temperature of the bonding tape, when the pressure within the vacuum bag is reduced.

Abstract: A method for implementing requests from an app by a SIM in a mobile phone comprises the steps of: binding an app to a BIP server by a mobile phone; delivering a request command to the BIP server from the mobile phone; converting the request command to an APDU format, packing the converted request command in the APDU format in a request packet, and delivering the request packet to an IP of a SIM by the BIP server; receiving and unpacking the request packet to have the converted request command, and providing the converted request command to the SIM; executing the request command to have a result by the SIM; delivering the result in a response packet to the BIP server via the mobile network relayed; unpacking the response packet to fetch the result, and delivering the result to the mobile phone for the app by the BIP server.

Abstract: An analysis cartridge and an analysis method, the analysis cartridge includes a first cover, a second cover, containers, a fluid tunnels and a rotary valve. The second cover has two opposite surfaces, a plurality of first through holes and a second through hole individually penetrate through the two opposite surfaces, and the first cover is attached to the second cover. The plurality of containers are disposed between the first cover and the second cover, with each of the containers being aligned to and filled in the first through holes. The plurality of the fluid tunnels is disposed on the first cover, and each of which is individually connected with a first pipette. The rotary valve is rotably disposed between the first cover and the second cover to correspond to the second through hole, and a flow channel disposed on the rotary valve is connected with the containers individually.

Abstract: A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.

Abstract: An anti-fuse array includes first through fourth adjacent anti-fuse bit columns, the anti-fuse bits of the first and second anti-fuse bit columns including portions of active areas of a first active area column, and the anti-fuse bits of the third and fourth anti-fuse bit columns including portions of active areas of a second active area column. Each row of a first set of conductive segment rows includes first and second conductive segments positioned between adjacent active areas of the first active area column and a third conductive segment positioned between adjacent active areas of the second active area column. Each row of a second set of conductive segments alternating with the first set of conductive segment rows includes a fourth conductive segment positioned between adjacent active areas of the first active area column and fifth and sixth conductive segments positioned between adjacent active areas of the second active area column.

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

Abstract: The disclosure provides a digital-to-analog conversion device and an operation method thereof. The digital-to-analog conversion device includes a digital-to-analog conversion circuit and a slew rate enhancement circuit. The digital-to-analog conversion circuit is configured to convert a digital code into an analog voltage. An output terminal of the digital-to-analog conversion circuit outputs the analog voltage to a load circuit. A control terminal of the slew rate enhancement circuit is coupled to the digital-to-analog conversion circuit to receive a control voltage following the analog voltage. The slew rate enhancement circuit is coupled to the output terminal of the digital-to-analog conversion circuit. The slew rate enhancement circuit enhances the slew rate at the output terminal of the digital-to-analog conversion circuit based on the control voltage.

Abstract: The present disclosure is directed to motor system for a multi-RET actuator system. The motor system includes a rotor configured to rotate within an interior cavity of a stator, a drive shaft coupled to the rotor and to a drive assembly of the multi-RET actuator system, an annular disc surrounding the stator, the annular disc is coupled to the rotor such that rotation of the rotor causes simultaneous rotation of the annular disc, a plurality of spaced apart magnets embedded within the annular disc, a HALL effect sensor, and a motor speed controller in communication with the rotor and the HALL effect sensor. Methods for controlling the position and speed of a motor system are also described herein.

Abstract: A process tube device can detect the presence of any external materials that may reside within a fluid flowing in the tube. The process tube device detects the external materials in-situ which obviates the need for a separate inspection device to inspect the surface of a wafer after applying fluid on the surface of the wafer. The process tube device utilizes at least two methods of detecting the presence of external materials. The first is the direct measurement method in which a light detecting sensor is used. The second is the indirect measurement method in which a sensor utilizing the principles of Doppler shift is used. Here, contrary to the first method that at least partially used reflected or refracted light, the second method uses a Doppler shift sensor to detect the presence of the external material by measuring the velocity of the fluid flowing in the tube.

Abstract: Disclosed herein, are Zwitterion polymer conjugates. The conjugate comprises a Zwitterion polymer, a linker, and a therapeutic polypeptide. Also described herein, are compositions comprising the conjugates, methods of their preparation, methods of treating diseases with the conjugates or their compositions, and method of preventing aggregation of therapeutic proteins.

Abstract: A pre-cleaning technique described herein may be used to remove native oxides and/or other contaminants from a semiconductor device in a manner in which the likelihood of chopping, clipping, and/or sidewall spacer thickness reduction is reduced. As described herein, a protection layer is formed on a capping layer over a gate structure of a transistor. A pre-cleaning operation is then performed to remove native oxides from the top surface of a source/drain region of the transistor. In the pre-cleaning operation, the protection layer is consumed instead of the material of the capping layer. In this way, the use of the protection layer reduces the likelihood of removal of material from the capping layer and/or reduces the amount of material that is removed from the capping layer during the pre-cleaning operation.