Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex “double-T” layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features, including “double-T” features, for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. Both opaque field phase shift masks and complementary binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer are produced.

Abstract: A photolithographic mask used for defining a layer in an integrated circuit, or other work piece, where the layer comprises a pattern including a plurality of features to be implemented with phase shifting in phase shift regions is laid out including for patterns comprising high density, small dimension features, and for “full shift” patterns. The method includes identifying cutting areas for phase shift regions based on characteristics of the pattern. Next, the process cuts the phase shift regions in selected ones of the cutting areas to define phase shift windows, and assigns phase values to the phase shift windows. The phase shift values assigned comprise &phgr; and &thgr;, so that destructive interference is caused in transitions between adjacent phase shift windows having respective phase shift values of &phgr; and &thgr;. In the preferred embodiment, &phgr; is equal to approximately &thgr;+180 degrees.

Abstract: A method for producing a computer readable definition of photolithographic mask used to define a target pattern is provided. The phase shift mask patterns include phase shift windows, and the trim mask patterns include trim shapes, which have boundaries defined by such sets of line segments. For a particular pair of phase shift windows used to define a target feature in a target pattern, each of the phase shift windows in the pair can be considered to have a boundary that includes at least one line segment that abuts the target feature. Likewise, a complementary trim shape used in definition of the target feature, for example by including a transmissive region used to clear an unwanted phase transition between the particular pair of phase shift windows, includes at least one line segment that can be considered to abut the target feature.

Abstract: Mask and integrated circuit fabrication approaches are described to facilitate use of so called “full phase” masks. This facilitates use of masks where substantially all of a layout is defined using phase shifting. More specifically, exposure settings including relative dosing between the phase shift mask and the trim masks are described. Additionally, single reticle approaches for accommodating both masks are considered. In one embodiment, the phase shifting mask and the trim mask are exposed using the same exposure conditions, except for relative dosing. In another embodiment, the relative dosing between the phase and trim patterns is 1.0:r, 2.0<r<4.0. These approaches facilitate better exposure profiles for the resulting ICs and can thus improve chip yield and increase throughput by reducing the need to alter settings and/or switch reticles between exposures.

Abstract: A multi-image reticle used to form integrated circuitry comprises a two dimensional array of spaced images arranged in a matrix of controllably spaced rows and columns of images on a single reticle. No rotation of the reticle is required to expose various levels of circuitry on a semiconductor wafer. The wafer is held in a stepper device, which controllably positions the wafer under the desired image of the mask for exposure of a resist on the wafer. A movable aperture controls exposure through a selected image or mask pattern on the reticle. By controlling which image is used, and accurately positioning the wafer via the stepper, multiple images are accurately registered, leading to improvement in dimensions of circuitry and other structures formed on the wafer.

Abstract: A multi-image reticle used to form integrated circuitry comprises a two dimensional array of spaced images arranged in a matrix of controllably spaced rows and columns of images on a single reticle. No rotation of the reticle is required to expose various levels of circuitry on a semiconductor wafer. The wafer is held in a stepper device, which controllably positions the wafer under the desired image of the mask for exposure of a resist on the wafer. A movable aperture controls exposure through a selected image or mask pattern on the reticle. By controlling which image is used, and accurately positioning the wafer via the stepper, multiple images are accurately registered, leading to improvement in dimensions of circuitry and other structures formed on the wafer.

Abstract: Methods for forming self-aligned photosensitive material spacers about protruding structures in semiconductor devices. One embodiment of the invention is a method for forming a LDD structure, utilizing disposable photosensitive material spacers. A second embodiment of the invention includes a method for forming a transistor, having salicided source/drain regions, utilizing photosensitive polyimide spacers for forming the salicided source/drain regions, without disposing of the spacers. A third embodiment of the invention includes a method for creating an offset from a protruding structure on a semiconductor substrate, using disposable photosensitive material spacers.

Abstract: Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the overlapping shapes can be grouped together to identify shapes that should be processed together. For large layouts, growing and grouping the shapes can be time consuming. Therefore, an approach that uses bins can speed up the clustering process, thereby allowing the phase shifting to be performed in parallel on multiple computers. Additional efficiencies result if identical clusters are identified and processing time saved so that repeated clusters of shapes only undergo the computationally expensive phase shifter placement and assignment process a single time.

Abstract: A computer-implemented method for matching parameters of outputs generated by a first and second process. The first process generates a first output having a characteristic measurable by a first parameter, and the second process generates a second output having the characteristic measurable by a second parameter. A computer having a processing unit and memory is provided. The computer generates a first model of the first parameter for the first process and a second model of the second parameter for the second process. The computer generates a first simulated output of the first process using the first model. A correction, which is a function of the second model and which compensates for the effect of the second process on the second parameter, is applied to the first simulated output to obtain a corrected output. The second process is applied to the corrected output to generate with the computer thereby a third output matching the first parameter of the first output.

Abstract: A conductive blank enables election beam (e-beam) patterning rather than optical patterning for the phase level etch of a phase-shifting mask (PSM) photomask. The conductive blank includes a conductive layer between a chrome (pattern) layer and a quartz substrate. The chrome layer is patterned with in-phase and phased features, and then is recoated with a resist layer. An e-beam exposure tool exposes the resist layer over the phased features. The still intact conductive layer under the chrome layer dissipates any charge buildup in the resist layer during this process. A phase level etch then etches through the conductive layer and creates a pocket in the quartz. A subsequent isotropic etch through both the in-phase and phased features removes the conductive layer at the in-phase features and improves exposure radiation transmission intensity. Alternatively, a visually transparent conductive layer can be used, eliminating the need to etch through the in-phase features.

Abstract: A structure and method are provided to ensure self-aligned fabrication of a tri-tone attenuated phase-shifting mask. A sub-resolution, 0 degree phase, greater than 90% transmission rim is provided along the edge of an opaque region. The alignment of this sub-resolution rim with the opaque and attenuated regions of the mask is performed in a single patterning step. In one embodiment, a narrow opaque region can be replaced by a sub-resolution, 0 degree phase, greater than 90% transmission line.

Abstract: Techniques for fabricating a device include forming a fabrication layout such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Included are techniques that correct for proximity effects associated with an edge in a layout corresponding to a design layer. An evaluation point is determined for the edge based on a profile of amplitudes output from a proximity effects model along a transect. The transect includes a target edge in the design layer corresponding to the edge. It is then determined how to correct at least a portion of the edge for proximity effects based on an analysis at the evaluation point. In other techniques, a dissection length parameter is derived based on a profile of amplitudes output by a proximity effects model along a transect. The transect includes a second edge in a second layout.

Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of assist features and proximity correction features. The method includes applying an adjustment to a phase shift mask pattern including a first and a second phase shift window, and a control chrome with a control width, and/or to a trim mask pattern having a trim shape with a trim width based upon one or both of a rule based correction and a model based correction to improve a match between a resulting exposure pattern and a target feature.

Abstract: Methods and apparatuses for fully defining static random access memory (SRAM) using phase shifting layouts are described. The approach includes identifying that a layout includes SRAM cells and defining phase shifting regions in a mask description to fully define the SRAM cells. The phase conflicts between adjacent phase shifters are resolved by selecting cutting patterns designed for the SRAM shape and functional structure. Additionally, the transistor gates of the SRAM cells can be reduced in size relative to the original SRAM layout design. Thus, an SRAM cell can be lithographically printed with small, consistent critical dimensions including extremely small gate lengths resulting in higher yields and improved performance.

Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

Abstract: Stepped photoresist profiles provide various methods of forming profiles in an underlying substrate. The stepped photoresist profiles are formed in two layers of photoresist that are disposed over the substrate. The substrate is then etched twice using a respective opening in each photoresist layer to create a stepped profile in the substrate.

Abstract: Stepped photoresist profiles provide various methods of forming profiles in an underlying substrate. The stepped photoresist profiles are formed in two layers of photoresist that are disposed over the substrate. The substrate is then etched twice using a respective opening in each photoresist layer to create a stepped profile in the substrate.

Abstract: A method for forming a photomask including applying photoresist to a semiconductor substrate, exposing a first area of the photoresist to a first dosage of radiation, and exposing a second area of the photoresist to a second dosage of radiation. The first and second areas may be concurrently exposed. First and second regions of the photoresist are then removed to form first and second openings that have different depths in the photoresist. Such removal may be effected by developing the first and second areas of the photoresist. One of the openings may extend down to an insulating layer formed on the semiconductor substrate. A contact and/or trench etch may be performed to remove. a portion of the insulating layer. Conductive material may then be deposited in the opening so formed to form a contact, a via, or another electrically conductive element that communicates with a structure underlying the insulating layer.

Abstract: An electronically programmed mask is connected to an electronic device, such as a processor. In operation, a mask design is first entered into the processor. The processor controls a display of an image on the electronically programmed mask, wherein the display replicates conventional type masks. The electronically programmed mask is designed such that the display presented on its screen provides optical contrast and characteristics that are easily changed or reprogrammed by the processor. Electronically controlled masks provide the same patterns as mechanical type masks without requiring rigid, permanent type structures to form a desired pattern.

Abstract: Techniques provided for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Included are techniques that correct for proximity effects associated with an edge in a layout corresponding to the design layer.