Abstract: An electronic module is provided, in which a first metal layer, an insulating layer and a second metal layer are sequentially formed on side faces and a non-active face of an electronic component to serve as a capacitor structure, where the capacitor structure is exposed from an active face of the electronic component so that by directly forming the capacitor structure on the electronic component, a distance between the capacitor structure and the electronic component is minimized, such that the effect of suppressing impedance can be optimized.

Abstract: Provided is a method of manufacturing a semiconductor device including: providing a substrate having a memory cell region and a logic region; forming a plurality of stack structures on the substrate in the memory cell region; forming a polysilicon layer to cover the plurality of stack structures and the substrate in the logic region; performing a chemical-mechanical polishing (CMP) process on the polysilicon layer to expose top surfaces of the plurality of stack structures; and after performing the CMP process, patterning the polysilicon layer to form an erase gate between adjacent two stack structures and form a logic gate on the substrate in the logic region, wherein the logic gate has a topmost top surface lower than a topmost top surface of the erase gate.

Abstract: A memory structure includes a substrate, a first word line and a first word line. The substrate has a plurality of active areas and an isolation structure surrounding the active areas. The first word line trench is formed across a first active area of the active areas and the isolation structure. The first word line trench includes a first slot and a first groove. The first slot is recessed from a top surface of the substrate. The first groove expands from a bottom of the first slot. A first sidewall is connected between the bottom of the first slot and a top of the first groove. A first word line is formed in the first word line trench. The first word line comprises a gate dielectric confomally formed on the first groove and the first slot.

Abstract: An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.

Abstract: A locking device for connecting a first housing to a second housing is provided, wherein the first housing and the second housing are arranged along a first direction. The locking mechanism includes a first hook, a second hook, a movable member, and a driving member. The first hook and the second hook are affixed to the first housing, and respectively have a first engaging recess and a second engaging recess. The first engaging recess and the second engaging recess are arranged along the first direction. The movable portion has an engaging portion. The driving member is connected to the second housing and the movable member, and is configured to drive the movable member to move relative to the second housing. When the first housing is affixed to the second housing via the locking mechanism, the engaging portion is accommodated in the first engaging recess.

Abstract: A convective polymerase chain reaction apparatus and an optical detecting method thereof are provided. The optical detecting method includes the following steps. A substance in a tube to be tested is heated. At least two monochromatic lights are provided and are combined using a light combining element to irradiate the tube to be tested. At least two excited lights generated by exciting the substance in the tube to be tested by the at least two monochromatic lights are sensed.

Abstract: A driving circuit includes at least one light-emitting element, a drive line, a data line, a touch sensor, and a read line. The drive line is electrically coupled to a first terminal of the at least one light-emitting element. The data line is electrically coupled to a second terminal of the at least one light-emitting element. The drive line is electrically coupled to a first terminal of the touch sensor. The read line is electrically coupled to a second terminal of the touch sensor. The read line is electrically isolated from the data line.

Abstract: The present disclosure provides a semiconductor device having a buried wordline. The semiconductor device includes a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.

Abstract: The present disclosure provides an anti-immune-checkpoint nanobody that specifically binds to a programmed cell death ligand 1. The present disclosure also provides the nucleic acid sequence of the anti-immune-checkpoint nanobody, use of the anti-immune-checkpoint nanobody for treating cancer and immune-related disorders, and a method for detecting expression levels of PD-L1.

Abstract: The present application provides a method of manufacturing a memory device having several word lines (WL) with reduced leakage. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation surrounding the active area; forming a first recess extending into the semiconductor substrate and across the active area; forming a first lining portion of a first insulating layer conformal to the first recess; disposing a first conductive material conformal to the first lining portion; forming a first conductive member surrounded by the first conductive material; disposing a second conductive material over the first conductive member to form a first conductive layer enclosing the first conductive member; and forming a first protruding portion of the first insulating layer above the first conductive layer and the first conductive member.

Abstract: The present application provides a memory device having several word lines (WL) with reduced leakage and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with an active area and including a recess extending into the semiconductor substrate; and a word line disposed within the recess, wherein the word line includes an insulating layer disposed within the recess, a conductive layer surrounded by the insulating layer, and a conductive member enclosed by the conductive layer, and the insulating layer includes a lining portion conformal to the recess and a protruding portion disposed above the conductive layer. A method of manufacturing the memory device is also disclosed.

Abstract: The present disclosure provides a semiconductor device having a buried wordline. The semiconductor device includes a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device having a buried wordline. The method includes forming a first recessed portion in a first dielectric layer in a substrate; forming a second recessed portion spaced apart from the first recessed portion and in the substrate; disposing a protection layer on the substrate to cover the second recessed portion; and disposing a second dielectric layer on the first dielectric layer.

Abstract: A displayed light-adjustment device includes two light-transmitting layers which are arranged oppositely, a display module, and an adjustable light-shading layer. The display module is stacked between the light-transmitting layers. The adjustable light-shading layer is interposed between the first light-transmitting layer and the display module, and the light transmittance of the adjustable light-shading layer is adjustable. When the adjustable light-shading layer is powered off, the light transmittance of the adjustable light-shading layer is greater than 75%, and when the adjustable light-shading layer is powered on, an ultraviolet resistance value of the adjustable light-shading layer is greater than 99%.

Abstract: Systems and methods for monitoring the quality of a surface treatment applied to an article in a manufacturing process are provided. A surface treatment may be applied to at least a portion of an article. A thermal profile of the article may be obtained and used to determine temperature indications of different regions of the article to which the surface treatment has been applied. A standard model of the article may be obtained that includes model regions having model temperature ranges. The temperature indications of the article can be compared with the model temperature ranges to determine if any temperature indications are outside of a corresponding model temperature range. The article may be a shoe part. The surface treatments may include the application of heat, plasma, dye, paint, primer, and/or the application of other materials, substances, and/or processes.

Abstract: The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.

Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.

Abstract: An electronic device includes a substrate, at least one electronic element and a heat dissipating electromagnetic shielding structure. The heat dissipating electromagnetic shielding structure is disposed on the substrate and covers the at least one electronic element, wherein the heat dissipating electromagnetic shielding structure includes a shielding frame and a heatsink. The shielding frame includes a plurality of spring members. The spring members are bent toward the substrate and partially abut against the heatsink. When the heatsink and the shielding frame are correspondingly arranged, a shielding space is defined, the electronic element is disposed in the shielding space, and a heat generated by the at least one electronic element is conducted out of the shielding space via the heatsink.

Abstract: A device and method of simultaneously removing flammable gases and nitrous oxide are provided. The device includes a thermal oxidation chamber, a high-temperature resistant dust filter, and a catalyst chamber. The thermal oxidation chamber is configured to receive an exhaust gas from a process tool. The exhaust gas includes flammable gases and nitrous oxide. The thermal oxidation chamber has a first exhaust pipe to emit nitrous oxide and dust generated after the exhaust gas is thermally oxidized. The high-temperature resistant dust filter receives dust and nitrous oxide from the first exhaust pipe, wherein the high-temperature resistant dust filter has a filter fiber net and a second exhaust pipe, and the second exhaust pipe is configured to emit nitrous oxide. The catalyst chamber receives nitrous oxide from the second exhaust pipe, wherein the catalyst chamber has a nitrous oxide decomposition catalyst to decompose nitrous oxide into nitrogen and oxygen.

Abstract: A first communication device capable of selecting a bandwidth, includes a receiving module, for receiving a wireless signal from a second communication device according to a first bandwidth; a measurement module, coupled to the receiving module, for measuring a communication quality of the wireless signal; and a processing module, coupled to the measurement module, for selecting a second bandwidth according to the first bandwidth and the communication quality; and a transmission module, coupled to the processing module, for transmitting information of the second bandwidth to the second communication device, for the second communication device to transmit the wireless signal to the fist communication device according to the second bandwidth.