Patents by Inventor Chuan Wang

Chuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PROJECTOR, HEAT DISSIPATION MODULE, AND HEAT DISSIPATION FIN SET
    Publication number: 20180196337
    Abstract: A projector includes a casing, an optical engine module, and a heat dissipation module. The optical engine module is disposed in the casing. The heat dissipation module is disposed in the casing and includes a heat dissipation fin set. The heat dissipation fin set includes at least one heat dissipation fin and at least one turbulent structure. The heat dissipation fin has a surface. The surface includes a first turbulent region and a second turbulent region. The first turbulent region is adjacent to the second turbulent region. The turbulent structure is disposed at least one of the first turbulent region and the second turbulent region, and the turbulent structure protrudes from the surface. An opening is formed between a top end of the turbulent structure and the surface.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 12, 2018
    Applicant: Coretronic Corporation
    Inventors: Chi-Chuan Wang, Yung-Ming Li, Tsung-Ching Lin, Jhih-Hao Chen, Wei-Chi Liu, Shi-Wen Lin
  • HIGH DENSITY MEMORY CELL STRUCTURES
    Publication number: 20180190770
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.
    Type: Application
    Filed: February 27, 2018
    Publication date: July 5, 2018
    Inventors: Waikin LI, Chengwen PEI, Ping-Chuan WANG
  • Gate driving circuit with isolating switch for display device using the same
    Patent number: 10008171
    Abstract: A gate driving circuit is provided. The gate driving circuit includes multistage driving modules, where an Nth stage driving module includes a setting circuit, a first driving circuit, an isolating switch circuit, a second driving circuit and an anti-noise circuit. The setting circuit generates a first precharge signal according to a gate driving signal of an (N?2)th scan line or a start signal. The isolating switch circuit coupled between the first driving circuit and the second driving circuit provides a second precharge signal, so as to effectively avoid a flickering problem of a display image caused by a surge of the gate driving signal due to a coupling effect of a parasitic capacitance of the transistor and a bootstrap capacitor, and meanwhile the bootstrap capacitor is not used, so as to effectively reduce a bezel area.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: June 26, 2018
    Assignees: Chunghwa Picture Tubes, Ltd., National Chiao Tung University
    Inventors: Wei-Lien Sung, Han-Lung Liu, Wen-Chuan Wang, Chi-Liang Kuo, Yuan-Hao Chang, Wen-Che Wang, Po-Tsun Liu, Guang-Ting Zheng, Yu-Fan Tu
  • Switch and matching noise cancelling for switch low noise amplifier
    Patent number: 10008987
    Abstract: A low noise amplifier (LNA) reduces matching and switch noise. The LNA includes a main radio frequency signal path, an auxiliary radio frequency signal path and a phase shifter. The main path includes a first transistor and an inductor. The inductor is positioned between an input port of the LNA and the first transistor. The first transistor receives an input radio frequency signal via the inductor and provides a first amplified signal based on the input radio frequency signal. The auxiliary radio frequency signal path provides a second amplified signal for a noise cancellation mode based on the input radio frequency signal. The phase shifter applies a phase shift to an output signal of the LNA based on the first amplified signal and the second amplified signal.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: June 26, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Serkan Sayilir, Chuan Wang, Li-chung Chang, Kevin Hsi Huai Wang
  • POST DISTORTION CANCELLATION WITH PHASE SHIFTER DIODE FOR LOW NOISE AMPLIFIER
    Publication number: 20180175806
    Abstract: A low noise amplifier may include a post distortion cancellation block coupled to the low noise amplifier. The post distortion cancellation block may include a diode, and phase-shift logic. The phase-shift logic may be coupled in series with the diode.
    Type: Application
    Filed: May 1, 2017
    Publication date: June 21, 2018
    Inventors: Mohammad Sadegh MEHRJOO, Chuan WANG, Yanming XIAO, Li-chung CHANG, Kevin Hsi Huai WANG
  • SWITCH AND MATCHING NOISE CANCELLING FOR SWITCH LOW NOISE AMPLIFIER
    Publication number: 20180175805
    Abstract: A low noise amplifier (LNA) reduces matching and switch noise. The LNA includes a main radio frequency signal path, an auxiliary radio frequency signal path and a phase shifter. The main path includes a first transistor and an inductor. The inductor is positioned between an input port of the LNA and the first transistor. The first transistor receives an input radio frequency signal via the inductor and provides a first amplified signal based on the input radio frequency signal. The auxiliary radio frequency signal path provides a second amplified signal for a noise cancellation mode based on the input radio frequency signal. The phase shifter applies a phase shift to an output signal of the LNA based on the first amplified signal and the second amplified signal.
    Type: Application
    Filed: May 1, 2017
    Publication date: June 21, 2018
    Inventors: Serkan SAYILIR, Chuan WANG, Li-chung CHANG, Kevin Hsi Huai WANG
  • PREHEATING DEVICE FOR ENDOSCOPY
    Publication number: 20180160890
    Abstract: A preheating device for endoscopy includes a flexible bag, a plurality of first welded joint, and a mark member. The flexible bag is disposed with a saturated sodium acetate solution and a trigger. The flexible bag includes a closed circumference around the outer periphery thereof. The closed circumference includes a longer side and a shorter side next to each other. The plurality of the first welded joint is arranged into a folding line along a longitudinal direction, wherein every two adjacent first welded joints of the folding line forms a flowing space. The folding line is substantially parallel to the longer side. The first welded joint nearest to the shorter side is the last first welded joint, and the mark member is disposed on the flexible bag between the last first welded joint and the shorter side. The mark member is used for indicating a placement of an endoscopy.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 14, 2018
    Inventors: WEI-HSUN WANG, I-TING WANG, CHING-CHUAN WANG
  • OPTICAL LENS
    Publication number: 20180164555
    Abstract: An optical lens includes a first lens group with negative refractive power, a second lens group with positive refractive power, and an aperture stop disposed between the first lens group and the second lens group. A total number of lenses in the first lens group is less than three, and a total number of lenses in the second lens group is less than five. The second lens group includes a first lens, a second lens and a third lens arranged in order in a direction away from the aperture stop. Each of the first lens and the second lens is an aspheric lens, and one of the first lens and the second lens has a diffractive optical surface.
    Type: Application
    Filed: August 7, 2017
    Publication date: June 14, 2018
    Inventors: Yuan-Hung SU, Sheng-Tang LAI, Kuo-Chuan WANG, Norihisa SAKAGAMI
  • PLANAR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180166390
    Abstract: Provided is a planar package structure and its manufacturing method. The planar package structure totally packages a die to make the die unexposed and to protect the die from impact or scratch. Further, at least one conductive pad of the die is electronically connected to an external electronic circuit through a plurality of wiring patterns and through holes filled with conductive materials. Then, the die may be connected to the external electronic circuit and may be protected from impact or scratch.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventors: Chao-Ching Yu, Lin-Ta Chung, Hsi-Ying Yuan, Tung-Chuan Wang
  • LOW-NOISE AMPLIFIER WITH INTEGRATED WIDEBAND TRANSFORMER-BASED POWER SPLITTER
    Publication number: 20180167040
    Abstract: A wireless communication device includes a first low-noise amplifier (LNA). The wireless communication device also includes a first LNA load circuit coupled to an output of the LNA. The wireless communication device further includes a power splitter switchably coupled to the first LNA load circuit. The power splitter includes a negatively coupled transformer and is switchably coupled to multiple outputs.
    Type: Application
    Filed: May 26, 2017
    Publication date: June 14, 2018
    Inventors: Serkan SAYILIR, Chuan WANG, Kevin Hsi Huai WANG
  • On-chip randomness generation
    Patent number: 9985615
    Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kai D. Feng, Ping-Chuan Wang, Zhijian Yang, Emmanuel Yashchin
  • OPTICAL LENS
    Publication number: 20180143407
    Abstract: An optical lens includes two lens groups and an aperture stop. A total number of lenses with refractive power of the two lens groups is larger than three, and the two lens groups includes an aspheric lens with negative refractive power. The aperture stop is disposed between the two lens groups. The optical lens satisfies the following condition: 0.05>[y(?)?(EFL*sin ?)]/(EFL*sin ?)>?0.3, where ? denotes a half field of view, y(?) denotes an image height of an image plane for visible light with respect to the half field of view ?, and EFL denotes an effective focal length for visible light of the optical lens.
    Type: Application
    Filed: August 10, 2017
    Publication date: May 24, 2018
    Inventors: KUO-CHUAN WANG, SHENG-TANG LAI, HSIN-TE CHEN, CHEN-CHENG LEE
  • Zoom lens
    Patent number: 9971132
    Abstract: A zoom lens includes, in order from a magnified side to a minified side, a first lens group, an aperture stop, and a second lens group. The second lens group has at least one aspheric surface. The zoom lens satisfies the conditions: 0.1<Ic/TTLw<0.15 and TTLw/EFLw?10, where Ic denotes a radius of an image circle, TTLw denotes a total track length of the zoom lens in the wide configuration, and EFLw denotes an effective focal length of the zoom lens in the wide configuration.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: May 15, 2018
    Assignee: YOUNG OPTICS INC.
    Inventors: Ying-Hsiu Lin, Kuo-Chuan Wang
  • Internet protocol address management (IPAM) integration with a plurality of virtualization tiers in the virtual cloud using infrastructure metadata
    Patent number: 9973439
    Abstract: Processing infrastructure metadata information about a virtual resource of a virtual cloud is disclosed. Infrastructure metadata information is collected. The collected metadata information is about a virtual resource of a virtual cloud. A storage of infrastructure metadata information is updated. The updating of the storage of infrastructure metadata information is performed using the collected information.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: May 15, 2018
    Assignee: Infoblox Inc.
    Inventors: Soheil Eizadi, Steven Whittle, Chuan Wang
  • Driving circuit and driving method
    Patent number: 9966032
    Abstract: A driving circuit in this disclosure includes plural stages of shift register circuits. Every stage in the shift register circuits includes an enabling control circuit, a first output circuit, a second output circuit and a disabling control circuit. The enabling circuit is configured to control the voltage of the first operation node according to enabling signal. The first output unit is configured to generate the first driving signal according to the voltage of the first operation node and the first clock signal. The second output unit is configured to generate the second driving signal according to the voltage of the first operation node and the second clock signal. The disabling control unit is used to pull low the voltage of the first operation node and output terminal of the first and second output unit to the reference voltage according to the first, third, and fourth clock signals.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 8, 2018
    Assignee: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Han-Lung Liu, Wei-Lien Sung, Wen-Chuan Wang, Shao-Lun Chang, Shih-Chieh Lin
  • Nanowire-based vertical memory cell array having a back plate and nanowire seeds contacting a bit line
    Patent number: 9966431
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: May 8, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Waikin Li, Chengwen Pei, Ping-Chuan Wang
  • OPTICAL LENS
    Publication number: 20180120544
    Abstract: An optical lens includes a first lens group having negative refractive power, a second lens group having positive refractive power, and an aperture stop disposed between the first lens group and the second lens group. A total number of lenses of the two lens groups is less than 9. The first lens group has at least three lenses with refractive power and at least one aspheric lens. The second lens group has at least three lenses with refractive power and at least one aspheric lens. The first lens group includes a lens having positive refractive power and an Abbe number of smaller 20.
    Type: Application
    Filed: June 20, 2017
    Publication date: May 3, 2018
    Inventors: Bing-Ju CHIANG, Yuan-Hung SU, Kuo-Chuan WANG
  • METHOD FOR FABRICATING ELECTROCHROMIC DEVICE
    Publication number: 20180120662
    Abstract: The present invention discloses a method for fabricating an electrochromic device, which adopts the vacuum cathodic arc-plasma deposition to comprise five layers with an ionic conduction layer (electrolyte) in contact with an electrochromic (EC) layer and an ion storage (complementary) layer, all sandwiched between two transparent conducting layers sequentially on a substrate. The method owns superior deposition efficiency and the fabricated thin film structures have higher crystalline homogeneity. In addition, thanks to the nanometer pores in the thin film structures, the electric capacity as well as the ion mobility are greater. Consequently, the reaction efficiency for bleaching or coloring is enhanced.
    Type: Application
    Filed: August 7, 2017
    Publication date: May 3, 2018
    Inventors: PO-WEN CHEN, CHEN-TE CHANG, PENG YANG, JIN-YU WU, DER-JUN JAN, CHENG-CHANG HSIEH, WEN-FA TSAI, MIN-CHUAN WANG
  • High density capacitor structure and method
    Patent number: 9960226
    Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Multilayer Films and Methods of Making the Same
    Publication number: 20180104942
    Abstract: Disclosed are multilayer films which can provide desired film performance suited for packaging applications favoring cost-effectiveness.
    Type: Application
    Filed: March 17, 2015
    Publication date: April 19, 2018
    Inventors: Zhi-Yi Shen, Zhen-Yu Zhu, Xiao-Chuan Wang, Ying Zou, Xuanyi Tang